S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 220
S912XEP768J5MAGR
Manufacturer Part Number
S912XEP768J5MAGR
Description
16-bit Microcontrollers - MCU 16-bit 768K Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XEP768J5MAGR
Rohs
yes
Core
HCS12X
Processor Series
MC9S12
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
768 KB
Data Ram Size
48 KB
On-chip Adc
Yes
Operating Supply Voltage
3.3 V to 5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-144
Mounting Style
SMD/SMT
Available stocks
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Chapter 3 Memory Mapping Control (S12XMMCV4)
in the memory map. This is to make sure that the correct PPAGE value will be present on stack at the time
of the RTC instruction execution.
3.5.2
Registers used for emulation purposes must be rebuilt by the in-circuit emulator hardware to achieve full
emulation of single chip mode operation. These registers are called port replacement registers (PRRs) (see
Table
aligned, word-misaligned and byte).
Each access to PRRs will be extended to 2 bus cycles for write or read accesses independent of the
operating mode. In emulation modes all write operations result in simultaneous writing to the internal
registers (peripheral access) and to the emulated registers (external access) located in the PRU in the
emulator. All read operations are performed from external registers (external access) in emulation modes.
In all other modes the read operations are performed from the internal registers (peripheral access).
Due to internal visibility of CPU accesses the CPU will be halted during XGATE or BDM access to any
PRR. This rule applies also in normal modes to ensure that operation of the device is the same as in
emulation modes.
A summary of PRR accesses:
220
•
•
•
1-25). PRRs are accessible from CPU, BDM and XGATE using different access types (word
An aligned word access to a PRR will take 2 bus cycles.
A misaligned word access to a PRRs will take 4 cycles. If one of the two bytes accessed by the
misaligned word access is not a PRR, the access will take only 3 cycles.
A byte access to a PRR will take 2 cycles.
Port Replacement Registers (PRRs)
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor
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