S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 472

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S912XEP768J5MAGR

Manufacturer Part Number
S912XEP768J5MAGR
Description
16-bit Microcontrollers - MCU 16-bit 768K Flash
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XEP768J5MAGR

Rohs
yes
Core
HCS12X
Processor Series
MC9S12
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
768 KB
Data Ram Size
48 KB
On-chip Adc
Yes
Operating Supply Voltage
3.3 V to 5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-144
Mounting Style
SMD/SMT

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
S912XEP768J5MAGR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
11.3
This section provides a detailed description of all registers accessible in the S12XECRG.
11.3.1
Figure 11-2
472
2. FORBYP and CTCTL are intended for factory test purposes only.
Address
0x000A
0x000B
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
FORBYP
Memory Map and Registers
POSTDIV
ARMCOP
CRGFLG
COPCTL
CRGINT
CLKSEL
PLLCTL
CTCTL
RTICTL
REFDV
SYNR
Name
Module Memory Map
gives an overview on all S12XECRG registers.
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
2
2
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
PLLSEL
RTDEC
WCOP
RTIE
Bit 7
RTIF
CME
Bit 7
VCOFRQ[1:0]
REFFRQ[1:0]
0
0
0
0
MC9S12XE-Family Reference Manual Rev. 1.25
= Unimplemented or Reserved
Figure 11-2. CRG Register Summary
RSBCK
PLLON
PORF
PSTP
RTR6
Bit 6
6
0
0
0
0
0
WRTMASK
XCLKS
RTR5
LVRF
FM1
Bit 5
5
0
0
0
0
0
0
NOTE
LOCKIF
LOCKIE
RTR4
FM0
Bit 4
4
0
0
0
0
0
FSTWKP
PLLWAI
LOCK
RTR3
Bit 3
3
0
0
0
0
0
SYNDIV[5:0]
REFDIV[5:0]
POSTDIV[4:0]
RTR2
ILAF
PRE
CR2
Bit 2
2
0
0
0
0
0
Freescale Semiconductor
RTIWAI
SCMIF
SCMIE
RTR1
PCE
CR1
Bit 1
1
0
0
0
COPWAI
SCME
RTR0
Bit 0
SCM
CR0
Bit 0
0
0
0
0

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