S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 201

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

3.3.2.6
Read: Anytime
Write: Anytime
These eight index bits are used to page 16 KByte blocks into the Flash page window located in the local
(CPU or BDM) memory map from address 0x8000 to address 0xBFFF (see
accessing up to 4 Mbytes of Flash (in the Global map) within the 64 KByte Local map. The PPAGE register
is effectively used to construct paged Flash addresses in the Local map format. The CPU has special access
to read and write this register directly during execution of CALL and RTC instructions..
Freescale Semiconductor
Address: 0x0015
PIX[7:0]
Reset
Field
7–0
W
R
PIX7
Program Page Index Bits 7–0 — These page index bits are used to select which of the 256 FLASH or ROM
array pages is to be accessed in the Program Page Window.
Program Page Index Register (PPAGE)
1
7
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Writes to this register using the special access of the CALL and RTC
instructions will be complete before the end of the instruction execution.
1
Bit21
PIX6
1
6
Figure 3-11. Program Page Index Register (PPAGE)
PPAGE Register [7:0]
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 3-12. PPAGE Address Mapping
Table 3-13. PPAGE Field Descriptions
PIX5
1
5
Global Address [22:0]
CAUTION
Bit14
PIX4
NOTE
1
4
Description
Bit13
PIX3
Address: CPU Local Address
1
3
Chapter 3 Memory Mapping Control (S12XMMCV4)
Address [13:0]
or BDM Local Address
PIX2
1
2
Figure
3-12). This supports
Bit0
PIX1
1
1
PIX0
0
0
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