S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 325

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

8.3.2.8.5
Read: Anytime. See
Write: If DBG not armed. See
8.3.2.8.6
Read: Anytime. See
Write: If DBG not armed. See
Freescale Semiconductor
Address: 0x002C
Address: 0x002D
Bits[15:8]
Bits[7:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
Bit 15
Comparator Data High Compare Bits — The Comparator data high compare bits control whether the selected
comparator compares the data bus bits [15:8] to a logic one or logic zero. The comparator data compare bits are
only used in comparison if the corresponding data mask bit is logic 1. This register is available only for
comparators A and C.
0 Compare corresponding data bit to a logic zero
1 Compare corresponding data bit to a logic one
Bit 7
Comparator Data Low Compare Bits — The Comparator data low compare bits control whether the selected
comparator compares the data bus bits [7:0] to a logic one or logic zero. The comparator data compare bits are
only used in comparison if the corresponding data mask bit is logic 1. This register is available only for
comparators A and C.
0 Compare corresponding data bit to a logic zero
1 Compare corresponding data bit to a logic one
0
0
7
7
Debug Comparator Data High Register (DBGXDH)
Debug Comparator Data Low Register (DBGXDL)
Table 8-29
Table 8-29
Figure 8-18. Debug Comparator Data High Register (DBGXDH)
Figure 8-19. Debug Comparator Data Low Register (DBGXDL)
Bit 14
Bit 6
0
0
6
6
Table 8-29
Table 8-29
MC9S12XE-Family Reference Manual Rev. 1.25
for visible register encoding.
for visible register encoding.
Table 8-35. DBGXAH Field Descriptions
Table 8-36. DBGXDL Field Descriptions
Bit 13
Bit 5
0
0
5
5
for visible register encoding.
for visible register encoding.
Bit 12
Bit 4
0
0
4
4
Description
Description
Bit 11
Bit 3
0
0
3
3
Chapter 8 S12X Debug (S12XDBGV3) Module
Bit 10
Bit 2
0
0
2
2
Bit 9
Bit 1
0
0
1
1
Bit 8
Bit 0
0
0
0
0
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