S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 488
S912XEP768J5MAGR
Manufacturer Part Number
S912XEP768J5MAGR
Description
16-bit Microcontrollers - MCU 16-bit 768K Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XEP768J5MAGR
Rohs
yes
Core
HCS12X
Processor Series
MC9S12
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
768 KB
Data Ram Size
48 KB
On-chip Adc
Yes
Operating Supply Voltage
3.3 V to 5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-144
Mounting Style
SMD/SMT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
S912XEP768J5MAGR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
11.4.1.2
The clock generator creates the clocks used in the MCU (see
on top of the individual clock gates indicates the dependencies of different modes (STOP, WAIT) and the
setting of the respective configuration bits.
The peripheral modules use the Bus Clock. Some peripheral modules also use the Oscillator Clock. If the
MCU enters Self Clock Mode (see
switched to PLLCLK running at its minimum frequency f
visible at the ECLK pin. The Core Clock signal is the clock for the CPU. The Core Clock is twice the Bus
Clock. But note that a CPU cycle corresponds to one Bus Clock.
IPLL clock mode is selected with PLLSEL bit in the CLKSEL register. When selected, the IPLL output
clock drives SYSCLK for the main system including the CPU and peripherals. The IPLL cannot be turned
off by clearing the PLLON bit, if the IPLL clock is selected. When PLLSEL is changed, it takes a
maximum of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks
freeze and CPU activity ceases.
488
EXTAL
XTAL
Condition
OSCILLATOR
Gating
System Clocks Generator
LOOP (IIPLL)
= Clock Gate
PHASE
LOCK
OSCCLK
PLLCLK
Monitor
Clock
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 11-16. System Clocks Generator
Section 11.4.2.2, “Self Clock
PLLSEL or SCM
1
0
1
0
SCM
STOP(PSTP, PCE),
STOP(PSTP, PRE),
WAIT(COPWAI),
WAIT(RTIWAI),
COP ENABLE
RTI ENABLE
SYSCLK
STOP
SCM
. The Bus Clock is used to generate the clock
Figure
STOP
Mode”) Oscillator clock source is
11-16). The gating condition placed
÷2
CLOCK PHASE
GENERATOR
COP
RTI
Freescale Semiconductor
Core Clock
Bus Clock
Oscillator
Clock
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