S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 486

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
11.4
11.4.1
11.4.1.1
The IPLL is used to run the MCU from a different time base than the incoming OSCCLK.
shows a block diagram of the IPLL.
For increased flexibility, OSCCLK can be divided in a range of 1 to 64 to generate the reference frequency
REFCLK using the REFDIV[5:0] bits. This offers a finer multiplication granularity. Based on the
SYNDIV[5:0] bits the IPLL generates the VCOCLK by multiplying the reference clock by a multiple of
2, 4, 6,... 126, 128. Based on the POSTDIV[4:0] bits the VCOCLK can be divided in a range of 1,2,4,6,8,...
to 62 to generate the PLLCLK.
Several examples of IPLL divider settings are shown in
settings are not recommended. The following rules help to achieve optimum stability and shortest lock
time:
486
.
•
•
EXTAL
XTAL
Use lowest possible f
Use highest possible REFCLK frequency f
Supplied by:
Functional Description
Functional Blocks
Phase Locked Loop with Internal Filter (IPLL)
Although it is possible to set the dividers to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
V
V
CONSUMPTION
DDPLL
DD
OSCILLATOR
REDUCED
/V
If (PLLSEL = 1) then f
IF POSTDIV = $00 the f
SS
/V
SSPLL
OSCCLK
VCO
MONITOR
f PLL
CLOCK
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 11-15. IPLL Functional Diagram
/ f
=
REF
2 f OSC
PROGRAMMABLE
×
REFERENCE
ratio (SYNDIV value).
REFDIV[5:0]
DIVIDER
BUS
PLL
PROGRAMMABLE
= f
SYNDIV[5:0]
×
DIVIDER
is identical to f
LOOP
----------------------------------------------------------------------------- -
[
PLL
REFDIV
NOTE
REF
/ 2.
REFCLK
.
Table
SYNDIV
FBCLK
+
1
] 2 POSTDIV
[
11-14. Shaded rows indicated that these
VCO
×
DETECTOR
DETECTOR
+
PHASE
1
LOCK
PDET
(divide by one)
PROGRAMMABLE
POSTDIV[4:0]
DIVIDER
POST
]
DOWN
UP
VCOCLK
LOCK
CPUMP
FILTER
AND
Freescale Semiconductor
V
DDPLL
Figure 11-15
/V
PLLCLK
SSPLL
VCO