S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 169

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

Freescale Semiconductor
Field
PTL
PTL
PTL
PTL
PTL
PTL
PTL
PTL
7
6
5
4
3
2
1
0
Port L general purpose input/output data—Data Register
Port L pin 7 is associated with the TXD signal of the SCI7 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port L general purpose input/output data—Data Register
Port L pin 6 is associated with the RXD signal of the SCI7 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port L general purpose input/output data—Data Register
Port L pin 5 is associated with the TXD signal of the SCI6 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port L general purpose input/output data—Data Register
Port L pin 4 is associated with the RXD signal of the SCI6 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port L general purpose input/output data—Data Register
Port L pin 3 is associated with the TXD signal of the SC5 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port L general purpose input/output data—Data Register
Port L pin 2 is associated with the RXD signal of the SCI5 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port L general purpose input/output data—Data Register
Port L pin 3 is associated with the TXD signal of the SCI4 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port L general purpose input/output data—Data Register
Port L pin 2 is associated with the RXD signal of the SCI4 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Table 2-88. PTL Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
Description
Chapter 2 Port Integration Module (S12XEPIMV1)
169