S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 197

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

3.3.2.3
Read: Anytime
Write: Anytime
The global page index register is used to construct a 23 bit address in the global map format. It is only used
when the CPU is executing a global instruction (GLDAA, GLDAB, GLDD, GLDS, GLDX,
GLDY,GSTAA, GSTAB, GSTD, GSTS, GSTX, GSTY) (see CPU Block Guide). The generated global
address is the result of concatenation of the CPU local address [15:0] with the GPAGE register [22:16] (see
Figure
Freescale Semiconductor
Address: 0x0010
GP[6:0]
Reset
Field
6–0
W
R
3-7).
Bit22
LDX
MOVB
GLDAA
Global Page Index Bits 6–0 — These page index bits are used to select which of the 128 64-kilobyte pages is
to be accessed.
Global Page Index Register (GPAGE)
0
0
7
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
GPAGE Register [6:0]
Example 3-1. This example demonstrates usage of the GPAGE register
#0x5000
#0x14, GPAGE
X
= Unimplemented or Reserved
GP6
0
6
Figure 3-6. Global Page Index Register (GPAGE)
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 3-7. GPAGE Address Mapping
Table 3-9. GPAGE Field Descriptions
GP5
0
5
;Set GPAGE offset to the value of 0x5000
;Initialize GPAGE register with the value of 0x14
;Load Accu A from the global address 0x14_5000
Global Address [22:0]
Bit16
CAUTION
Bit15
GP4
0
4
Description
GP3
0
3
CPU Address [15:0]
Chapter 3 Memory Mapping Control (S12XMMCV4)
GP2
0
2
GP1
0
1
Bit 0
GP0
0
0
197