S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 524

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
Only analog input signals within the potential range of V
in a non-railed digital output code.
13.4.2
This subsection explains some of the digital features in more detail. See
Descriptions”
13.4.2.1
The external trigger feature allows the user to synchronize ATD conversions to the external environment
events rather than relying on software to signal the ATD module when ATD conversions are to take place.
The external trigger signal (out of reset ATD channel 15, configurable in ATDCTL1) is programmable to
be edge or level sensitive with polarity control.
combinations of control bits and their effect on the external trigger function.
During a conversion, if additional active edges are detected the overrun error flag ETORF is set.
In either level or edge triggered modes, the first conversion begins when the trigger is received.
Once ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be
triggered externally.
If the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion
sequence, this does not constitute an overrun. Therefore, the flag is not set. If the trigger is left asserted in
level mode while a sequence is completing, another sequence will be triggered immediately.
524
Digital Sub-Block
External Trigger Input
ETRIGLE
for all details.
X
X
0
0
1
1
ETRIGP
X
X
0
1
0
1
MC9S12XE-Family Reference Manual Rev. 1.25
Table 13-23. External Trigger Control Bits
ETRIGE
0
0
1
1
1
1
Table 13-23
SCAN
X
X
X
X
0
1
RL
Ignores external trigger. Performs one
conversion sequence and stops.
Ignores external trigger. Performs
continuous conversion sequences.
Falling edge triggered. Performs one
conversion sequence per trigger.
Rising edge triggered. Performs one
conversion sequence per trigger.
Trigger active low. Performs continuous
conversions while trigger is active.
Trigger active high. Performs continuous
conversions while trigger is active.
to V
gives a brief description of the different
RH
(A/D reference potentials) will result
Description
Section 13.3.2, “Register
Freescale Semiconductor