S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 801

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S912XEP768J5MAGR

Manufacturer Part Number
S912XEP768J5MAGR
Description
16-bit Microcontrollers - MCU 16-bit 768K Flash
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XEP768J5MAGR

Rohs
yes
Core
HCS12X
Processor Series
MC9S12
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
768 KB
Data Ram Size
48 KB
On-chip Adc
Yes
Operating Supply Voltage
3.3 V to 5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-144
Mounting Style
SMD/SMT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S912XEP768J5MAGR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Read: Anytime
Write: Anytime.
22.3.2.10 Timer Interrupt Enable Register (TIE)
Read: Anytime
Write: Anytime.
Freescale Semiconductor
Module Base + 0x000C
EDGnB
EDGnA
C7I:C0I
Reset
Field
Field
7:0
7:0
W
R
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits.
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
C7I
0
7
C6I
0
6
EDGnB
Figure 22-18. Timer Interrupt Enable Register (TIE)
Table 22-12. Edge Detector Circuit Configuration
0
0
1
1
Table 22-11. TCTL3/TCTL4 Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
Table 22-13. TIE Field Descriptions
C5I
EDGnA
0
5
0
1
0
1
Capture on any edge (rising or falling)
C4I
0
4
Capture on falling edges only
Capture on rising edges only
Description
Description
Capture disabled
Configuration
Chapter 22 Timer Module (TIM16B8CV2) Block Description
C3I
0
3
C2I
0
2
C1I
0
1
C0I
0
0
801

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