S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 228

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

Chapter 4 Memory Protection Unit (S12XMPUV1)
access is allowed or represents an access violation. If an access violation caused by the S12X CPU is
detected, the MPU module raises an access violation interrupt. If the MPU module detects an access
violation caused by a bus master other than the S12X CPU, it flags an access error condition to the
respective master. In addition to the restrictions defined for memory ranges in the MPU descriptors,
accesses to memory not covered by any MPU descriptor (even read accesses!) are considered access
violations.
Figure 4-1
4.1.3
1. Master 3 can be implemented or left out depending the chip configuration. Please refer to the Device Reference Manual for
information about the availability and function of Master 3.
228
•
•
CPU
XGATE
“Master3”
Protects memory from undesired accesses coming from up to 3 bus masters
Eight memory protection descriptors
— each descriptor can cover the full global memory map (8 MBytes)
— each descriptor has a granularity of 8 Bytes
Data Access
Op-code Fetch
Data Access
Op-code Fetch
Data Access
shows a block diagram of the MPU module.
Features
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 4-1. Block Diagram
Access Validation
Access Validation
Access Validation
MPU Monitoring
MPU Monitoring
MPU Monitoring
MMC
Access Violation
Interrupt
1
Freescale Semiconductor
Registers
Status
MPU