S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 317
S912XEP768J5MAGR
Manufacturer Part Number
S912XEP768J5MAGR
Description
16-bit Microcontrollers - MCU 16-bit 768K Flash
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEG128J2MAL.pdf
(1324 pages)
Specifications of S912XEP768J5MAGR
Rohs
yes
Core
HCS12X
Processor Series
MC9S12
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
768 KB
Data Ram Size
48 KB
On-chip Adc
Yes
Operating Supply Voltage
3.3 V to 5 V
Operating Temperature Range
- 40 C to + 125 C
Package / Case
LQFP-144
Mounting Style
SMD/SMT
Available stocks
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Price
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Part Number:
S912XEP768J5MAGR
Manufacturer:
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10 000
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8.3.2.7
There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if
transitions from that state are allowed, depending upon comparator matches or tag hits, and defines the
next state for the state sequencer following a match. The three debug state control registers are located at
the same address in the register address map (0x0027). Each register can be accessed using the COMRV
bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag register
(DBGMFR).
8.3.2.7.1
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and S12XDBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the
targeted next state whilst in State1. The matches refer to the match channels of the comparator match
control logic as depicted in
by setting the comparator enable bit in the associated DBGXCTL control register.
Freescale Semiconductor
Address: 0x0027
SC[3:0]
Reset
Field
3–0
SC[3:0]
W
R
0000
0001
0010
These bits select the targeted next state whilst in State1, based upon the match event.
Debug State Control Registers
0
0
7
Debug State Control Register 1 (DBGSCR1)
= Unimplemented or Reserved
Figure 8-9. Debug State Control Register 1 (DBGSCR1)
0
0
6
Table 8-21. State Control Register Access Encoding
Figure 8-1
Table 8-23. State1 Sequencer Next State Selection
COMRV
MC9S12XE-Family Reference Manual Rev. 1.25
Table 8-22. DBGSCR1 Field Descriptions
00
01
10
11
0
0
5
and described in
Any match triggers to Final State
Visible State Control Register
Any match triggers to state2
Any match triggers to state3
0
0
4
Description
Section
Description
DBGSCR1
DBGSCR2
DBGSCR3
DBGMFR
SC3
0
3
8.3.2.8.1. Comparators must be enabled
Chapter 8 S12X Debug (S12XDBGV3) Module
SC2
0
2
SC1
0
1
SC0
0
0
317
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