S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 738

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

Chapter 20 Serial Communication Interface (S12SCIV5)
20.3.2.9
Read: Anytime; reading accesses SCI receive data register
Write: Anytime; writing accesses SCI transmit data register; writing to R8 has no effect
738
Module Base + 0x0006
Module Base + 0x0007
SCIDRH
SCIDRH
SCIDRL
Reset
Reset
R[7:0]
T[7:0]
Field
7:0
R8
T8
7
6
W
W
R
R
Received Bit 8 — R8 is the ninth data bit received when the SCI is configured for 9-bit data format (M = 1).
Transmit Bit 8 — T8 is the ninth data bit transmitted when the SCI is configured for 9-bit data format (M = 1).
R7:R0 — Received bits seven through zero for 9-bit or 8-bit data formats
T7:T0 — Transmit bits seven through zero for 9-bit or 8-bit formats
R8
R7
T7
SCI Data Registers (SCIDRH, SCIDRL)
0
0
7
7
If the value of T8 is the same as in the previous transmission, T8 does not
have to be rewritten.The same value is transmitted until T8 is rewritten
In 8-bit data format, only SCI data register low (SCIDRL) needs to be
accessed.
When transmitting in 9-bit data format and using 8-bit write instructions,
write first to SCI data register high (SCIDRH), then SCIDRL.
= Unimplemented or Reserved
R6
T8
T6
0
0
6
6
Table 20-13. SCIDRH and SCIDRL Field Descriptions
Figure 20-12. SCI Data Registers (SCIDRH)
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 20-13. SCI Data Registers (SCIDRL)
R5
T5
0
0
0
5
5
NOTE
R4
T4
0
0
0
4
4
Description
R3
T3
0
0
0
3
3
R2
T2
0
0
0
2
2
Freescale Semiconductor
R1
T1
0
0
0
1
1
R0
T0
0
0
0
0
0