S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 379

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

10.5
10.5.1
XGATE threads are triggered by interrupt requests which are routed to the XGATE module (see
S12X_INT Section). Only a subset of the MCU’s interrupt requests can be routed to the XGATE. Which
specific interrupt requests these are and which channel ID they are assigned to is documented in Section
“Interrupts” of the device overview.
10.5.2
There are three types of interrupt requests which can be triggered by the XGATE module:
All outgoing XGATE interrupts, except software error interrupts, can be disabled by the XGIE bit in the
XGATE module control register (XGMCTL, see
(XGMCTL)”).
10.6
The XGATE debug mode is a feature to allow debugging of application code.
10.6.1
In debug mode the RISC core will be halted and the following debug features will be enabled:
1. Only possible if MCU is unsecured
Freescale Semiconductor
4. Channel interrupts
5. Software triggers
6. Software error interrupt
•
For each XGATE channel there is an associated interrupt flag in the XGATE interrupt flag vector
(XGIF, see
set through the "SIF" instruction by the RISC core. They are typically used to flag an interrupt to
the S12X_CPU when the XGATE has completed one of its task.
Software triggers are interrupt flags, which can be set and cleared by software (see
Section 10.3.1.9, “XGATE Software Trigger Register
trigger XGATE tasks by the S12X_CPU software. However these interrupts can also be routed to
the S12X_CPU (see S12X_INT Section) and triggered by the XGATE software.
The software error interrupt signals to the S12X_CPU the detection of an error condition in the
XGATE application code (see
interrupt. Executing the interrupt service routine will automatically reset the interrupt line.
Read and Write accesses to RISC core registers (XGCCR, XGPC, XGR1–XGR7)
All RISC core registers can be modified. Leaving debug mode will cause the RISC core to continue
program execution with the modified register values.
Interrupts
Debug Mode
Incoming Interrupt Requests
Outgoing Interrupt Requests
Debug Features
Section 10.3.1.8, “XGATE Channel Interrupt Flag Vector
MC9S12XE-Family Reference Manual Rev. 1.25
Section 10.4.5, “Software Error
Section 10.3.1.1, “XGATE Control Register
(XGSWT)”). They are typically used to
Detection”). This is a non-maskable
(XGIF)”). These flags can be
Chapter 10 XGATE (S12XGATEV3)
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