S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 312

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

Chapter 8 S12X Debug (S12XDBGV3) Module
8.3.2.2
Read: Anytime
Write: Never
312
Address: 0x0021
SSF[2:0]
Reset
EXTF
Field
POR
TBF
2–0
7
6
W
R
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was
last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits CNT[6:0].
The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset
initialization. Other system generated resets have no affect on this bit.
External Tag Hit Flag — The EXTF bit indicates if a tag hit condition from an external TAGHI/TAGLO tag was
met since arming. This bit is cleared when ARM in DBGC1 is written to a one.
0 External tag hit has not occurred
1 External tag hit has occurred
State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During
a debug session on each transition to a new state these bits are updated. If the debug session is ended by
software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer
before disarming. If a debug session is ended by an internal trigger, then the state sequencer returns to state0
and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state
sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See
TBF
Debug Status Register (DBGSR)
—
0
7
= Unimplemented or Reserved
EXTF
Table 8-9. SSF[2:0] — State Sequence Flag Bit Encoding
0
0
6
101,110,111
Figure 8-4. Debug Status Register (DBGSR)
SSF[2:0]
MC9S12XE-Family Reference Manual Rev. 1.25
000
001
010
011
100
Table 8-8. DBGSR Field Descriptions
0
0
0
5
0
0
0
4
Description
State0 (disarmed)
Current State
Final State
Reserved
0
0
0
State1
State2
State3
3
SSF2
Table 8-9
0
0
2
.
Freescale Semiconductor
SSF1
0
0
1
SSF0
0
0
0