S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 172

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

1. Read: Anytime.
1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.98
2.3.99
172
Address 0x0375
Address 0x0376
Write: Anytime.
Write: Anytime.
WOML
PPSL
Field
Field
Reset
Reset
7-0
7-0
W
W
R
R
Port L pull device select—Determine pull device polarity on input pins
This register selects whether a pull-down or a pull-up device is connected to the pin.
1 A pull-down device is connected to the associated pin, if enabled and if the pin is used as input.
0 A pull-up device is connected to the associated pin, if enabled and if the pin is used as input.
Port L wired-or mode—Enable wired-or functionality
This register configures the output pins as wired-or independent of the function used on the pins. If enabled the
output is driven active low only (open-drain). A logic level of “1” is not driven.This allows a multipoint connection of
several serial modules. These bits have no influence on pins used as inputs.
1 Output buffers operate as open-drain outputs.
0 Output buffers operate as push-pull outputs.
WOML7
PPSL7
Port L Polarity Select Register (PPSL)
Port L Wired-Or Mode Register (WOML)
0
0
7
7
WOML6
PPSL6
0
0
6
6
Figure 2-97. Port L Wired-Or Mode Register (WOML)
Figure 2-96. Port L Polarity Select Register (PPSL)
Table 2-94. WOML Register Field Descriptions
Table 2-93. PPSL Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
WOML5
PPSL5
0
0
5
5
WOML4
PPSL4
0
0
4
4
Description
Description
WOML3
PPSL3
3
0
3
0
WOML2
PPSL2
0
0
2
2
Access: User read/write
Access: User read/write
WOML1
Freescale Semiconductor
PPSL1
0
0
1
1
WOML0
PPSL0
0
0
0
0
(1)
(1)