S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 381

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

10.6.2
Debug mode can only be left by setting the XGDBG bit to "0". If a thread is active (XGCHID has not been
cleared in debug mode), program execution will resume at the value of XGPC.
10.7
In order to protect XGATE application code on secured S12X devices, a few restrictions in the debug
features have been made. These are:
Freescale Semiconductor
2. Software breakpoints
3. Tagged Breakpoints
4. Forced Breakpoints
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Writing a "1" to XGDBG and XGDBGM in the same write access causes the XGATE to enter
debug mode upon completion of the current instruction.
XGATE programs which are stored in the internal RAM allow the use of software breakpoints. A
software breakpoint is set by replacing an instruction of the program code with the "BRK"
instruction.
As soon as the program execution reaches the "BRK" instruction, the XGATE enters debug mode.
Additionally a software breakpoint request is sent to the S12X_DBG module (see section 4.9 of
the S12X_DBG Section).
Upon entering debug mode, the program counter will point to the "BRK" instruction. The other
RISC core registers will hold the result of the previous instruction.
To resume program execution, the "BRK" instruction must be replaced by the original instruction
before leaving debug mode.
The S12X_DBG module is able to place tags on fetched opcodes. The XGATE is able to enter
debug mode right before a tagged opcode is executed (see section 4.9 of the S12X_DBG Section).
Upon entering debug mode, the program counter will point to the tagged instruction. The other
RISC core registers will hold the result of the previous instruction.
Forced breakpoints are triggered by the S12X_DBG module (see section 4.9 of the S12X_DBG
Section). When a forced breakpoint occurs, the XGATE will enter debug mode upon completion
of the current instruction.
Registers XGCCR, XGPC, and XGR1–XGR7 will read zero on a secured device
Registers XGCCR, XGPC, and XGR1–XGR7 can not be written on a secured device
Single stepping is not possible on a secured device
Security
Leaving Debug Mode
After writing to the XGDBG bit the XGATE will not immediately enter
debug mode. Depending on the instruction that is executed at this time there
may be a delay of several clock cycles. The XGDBG will read "0" until
debug mode is entered.
MC9S12XE-Family Reference Manual Rev. 1.25
NOTE
Chapter 10 XGATE (S12XGATEV3)
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