S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 592

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
15.3.1.5
In master transmit mode, when data is written to the IBDR a data transfer is initiated. The most significant
bit is sent first. In master receive mode, reading this register initiates next byte data receiving. In slave
mode, the same functions are available after an address match has occurred.Note that the Tx/Rx bit in the
IBCR must correctly reflect the desired direction of transfer in master and slave modes for the transmission
to begin. For instance, if the IIC is configured for master transmit but a master receive is desired, then
reading the IBDR will not initiate the receive.
Reading the IBDR will return the last byte received while the IIC is configured in either master receive or
slave receive modes. The IBDR does not reflect every byte that is transmitted on the IIC bus, nor can
software verify that a byte has been written to the IBDR correctly by reading it back.
In master transmit mode, the first byte of data written to IBDR following assertion of MS/SL is used for
the address transfer and should com.prise of the calling address (in position D7:D1) concatenated with the
required R/W bit (in position D0).
592
Reset
RXAK
Field
SRW
IBIF
2
1
0
W
R
Module Base + 0x0004
Slave Read/Write — When IAAS is set this bit indicates the value of the R/W command bit of the calling address
sent from the master
This bit is only valid when the I-bus is in slave mode, a complete address transfer has occurred with an address
match and no other transfers have been initiated.
Checking this bit, the CPU can select slave transmit/receive mode according to the command of the master.
0 Slave receive, master writing to slave
1 Slave transmit, master reading from slave
I-Bus Interrupt — The IBIF bit is set when one of the following conditions occurs:
It will cause a processor interrupt request if the IBIE bit is set. This bit must be cleared by software, writing a one
to it. A write of 0 has no effect on this bit.
Received Acknowledge — The value of SDA during the acknowledge bit of a bus cycle. If the received
acknowledge bit (RXAK) is low, it indicates an acknowledge signal has been received after the completion of 8
bits data transmission on the bus. If RXAK is high, it means no acknowledge signal is detected at the 9th clock.
0 Acknowledge received
1 No acknowledge received
D7
IIC Data I/O Register (IBDR)
0
7
— Arbitration lost (IBAL bit set)
— Data transfer complete (TCF bit set)
— Addressed as slave (IAAS bit set)
D6
0
6
Table 15-9. IBSR Field Descriptions (continued)
Figure 15-8. IIC Bus Data I/O Register (IBDR)
MC9S12XE-Family Reference Manual Rev. 1.25
D5
0
5
D4
0
4
Description
D3
0
3
D2
0
2
Freescale Semiconductor
D1
0
1
D0
0
0