SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 94

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 86.
[1]
Table 87.
Table 88.
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
15 to 9
8
7
6 to 5
4
3
2
1
0
Bit
Symbol
Reset
Access
The reset value depends on the corresponding OTG status. For details, see
Symbol
-
B_SE0_SRP
B_SESS_END
-
RMT_CONN
ID
DP_SRP
A_B_SESS_VLD
VBUS_VLD
OTG Status register (address 0378h) bit allocation
OTG Status register (address 0378h) bit description
OTG Interrupt Latch register (address set: 037Ch, clear: 037Eh) bit allocation
9.5.3.1 OTG Status register
9.5.3.2 OTG Interrupt Latch register
B_SESS_
9.5.3 OTG Interrupt registers
R/S/C
END
15
15
[1]
R
R
0
7
0
This register indicates the current state of the signals that can generate an interrupt. The
bit allocation of the register is given in
The OTG Interrupt Latch register indicates the source that generated the interrupt. The
status of this register bits depends on the settings of the Interrupt Enable Fall and
Interrupt Enable Rise registers, and the occurrence of the respective events.
The bit allocation of the register is given in
R/S/C
Description
reserved for future use
2 ms of SE0 detected in the B-idle state
V
reserved
Remote connect detection
ID pin digital input
DP asserted during SRP
A-session valid for the A-device. B-session valid for the B-device.
A-device V
14
14
R
R
BUS
0
6
0
0
reserved
< 0.8 V
BUS
R/S/C
13
valid comparator, indicates V
13
R
R
0
5
0
0
Rev. 01 — 18 November 2009
reserved
reserved
[1]
CONN
RMT_
R/S/C
12
12
R
R
0
4
0
0
Table
Table
Table
R/S/C
86.
11
11
ID
[1]
R
R
0
3
0
BUS
87.
88.
> 4.4 V
DP_SRP
10
10
R
R
R
0
2
0
0
Hi-Speed USB OTG controller
OTG_TMR_
A_B_SESS
TIMEOUT
R/S/C
_VLD
[1]
R
R
9
0
1
9
0
SAF1761
© NXP B.V. 2009. All rights reserved.
VBUS_VLD
B_SE0_
B_SE0_
R/S/C
SRP
SRP
94 of 166
[1]
R
R
8
0
0
8
0