SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 104

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 102. Interrupt Configuration register (address 0210h) bit allocation
Table 103. Interrupt Configuration register (address 0210h) bit description
Table 104. Debug mode settings
[1]
Table 105. Debug register (address 0212h) bit allocation
[1]
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
7 to 6
5 to 4
3 to 2
1
0
Value
00h
01h
1Xh
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
First NAK: The first NAK on an IN or OUT token after a previous ACK response.
The reserved bits should always be written with the reset value.
Symbol
CDBGMOD[1:0]
DDBGMODIN[1:0]
DDBGMODOUT[1:0]
INTLVL
INTPOL
CDBGMOD
interrupt on all ACK and NAK
interrupt on all ACK
interrupt on all ACK and first NAK
10.3.4 Debug register
R/W
R/W
R/W
15
CDBGMOD[1:0]
7
1
1
0
0
7
0
0
Bit INTPOL controls the signal polarity of the INT output: active HIGH or LOW, rising or
falling edge. For level-triggering, bit INTLVL must be made logic 0. By setting INTLVL to
logic 1, an interrupt will generate a pulse of 60 ns (edge-triggering).
This register can be accessed using address 0212h in 16-bit bus access mode or using
the upper-two bytes of the Interrupt Configuration register in 32-bit bus access mode. For
the bit allocation, see
R/W
R/W
R/W
14
6
1
1
0
0
6
0
0
Description
Control 0 Debug Mode: For values, see
Data Debug Mode IN: For values, see
Data Debug Mode OUT: For values, see
Interrupt Level: Selects signaling mode on output INT: 0 = level; 1 = pulsed. In pulsed
mode, an interrupt produces a 60 ns pulse. Bus reset value: unchanged.
Interrupt Polarity: Selects the signal polarity on output INT: 0 = active LOW; 1 = active
HIGH. Bus reset value: unchanged.
[1]
DDBGMODIN[1:0]
R/W
R/W
R/W
13
5
1
1
0
0
5
0
0
Rev. 01 — 18 November 2009
DDBGMODIN
interrupt on all ACK and NAK
interrupt on ACK
interrupt on all ACK and first NAK
Table
105.
reserved
R/W
R/W
R/W
12
4
1
1
0
0
4
0
0
reserved
[1]
DDBGMODOUT[1:0]
[1]
R/W
R/W
R/W
11
3
1
1
0
0
3
1
1
Table 104
Table 104
Table 104
[1]
DDBGMODOUT
interrupt on all ACK, NYET and NAK
interrupt on ACK and NYET
interrupt on all ACK, NYET and first
NAK
R/W
R/W
R/W
10
2
1
1
0
0
2
0
0
Hi-Speed USB OTG controller
[1]
unchanged
INTLVL
R/W
R/W
R/W
1
0
9
0
0
1
0
0
SAF1761
© NXP B.V. 2009. All rights reserved.
unchanged
INTPOL
DEBUG
104 of 166
R/W
R/W
R/W
0
0
8
0
0
0
0
0