SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 21

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SAF1761_1
Product data sheet
of that burst. It will be reasserted shortly after the DACK de-assertion, as long as the DMA
transfer counter was not reached. DREQ will be de-asserted on the last cycle when the
DMA transfer counter is reached and will not be reasserted until the DMA reprogramming
is performed. Both DREQ and DACK signals are programmable as active LOW or active
HIGH, according to the system requirements.
The DMA start address must be initialized in the respective register, and the subsequent
transfers will automatically increment the internal SAF1761 memory address. A register or
memory access or access to other system memory can occur in between DMA bursts,
whenever the bus is released because DACK is de-asserted, without affecting the DMA
transfer counter or the current address.
Any memory area can be accessed by the systems DMA at any starting address because
there are no predefined memory blocks. The DMA transfer must start on a word or double
word address, depending on whether the data bus width is set to 16 bit or 32 bit. DMA is
the most efficient method to initialize the payload area, to reduce the CPU usage and
overall system loading.
The SAF1761 does not implement EOT to signal the end of a DMA transfer. If
programmed, an interrupt may be generated by the SAF1761 at the end of the DMA
transfer.
The slave DMA of the SAF1761 will issue a DREQ to the DMA controller of the system to
indicate that it is programmed for transfer and data is ready. The system DMA controller
may also start a transfer without the need of the DREQ, if the SAF1761 memory is
available for the data transfer and the SAF1761 DMA programming is completed.
It is also possible that the systems DMA will perform a memory-to-memory type of transfer
between the system memory and the SAF1761 memory. The SAF1761 will be accessed
in PIO mode. Consequently, memory read operations must be preceded by initializing the
Memory register (address 033Ch), as described in
generated by the SAF1761 on completing the DMA transfer but an internal processor
interrupt may be generated to signal that the DMA transfer is completed. This is mainly
useful in implementing the double-buffering scheme for data transfer to optimize the USB
bandwidth.
The SAF1761 DMA programming involves:
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Set the active levels of signals DREQ and DACK in the HW Mode Control register.
The DMA Start Address register contains the first memory address at which the data
transfer will start. It must be word-aligned in 16-bit data bus mode and double word
aligned in 32-bit data bus mode.
The programming of the HcDMAConfiguration register specifies:
– The type of transfer that will be performed: read or write.
– The burst size, expressed in bytes, is specified, regardless of the data bus width.
– The transfer length, expressed in number of bytes, defines the number of bursts.
For the same burst size, a double number of cycles will be generated in 16-bit
mode data bus width as compared to 32-bit mode.
The DREQ will be de-asserted and asserted to generate the next burst, as long as
there are bytes to be transferred. At the end of a transfer, the DREQ will be
de-asserted and an IRQ can be generated if DMAEOTINT (bit 3 in the HcInterrupt
register) is set. The maximum DMA transfer size is equal to the maximum memory
Rev. 01 — 18 November 2009
Section
Hi-Speed USB OTG controller
7.3.1. No IRQ will be
SAF1761
© NXP B.V. 2009. All rights reserved.
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