SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 150

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SAF1761_1
Product data sheet
18.4.2 Implication
18.4.3 Workaround
18.5.1 Problem description
18.5 Errata added on 2009-04-20
For low-power applications, the SAF1761 can be put into the suspend state on both the
Host Controller and Peripheral Controller sides. But to enter deep-sleep suspend mode,
the clock must be turned off so that the current consumption can be reduced to less than
400 A. For such applications, this issue is serious because the SAF1761 can no longer
be resumed, and the only way to recover is to remove and re-apply power to the chip.
The problem can be worked around by connecting the CLKIN pin to GNDD (digital
ground). At the system level, ensure that the V
the same time to the SAF1761 (i.e. both V
supply of 3.3 V). Alternatively, V
workaround will be ineffective.
The value written to the Endpoint Index (022Ch) and Control Function (0228h)
registers cannot be read-back correctly.
If there is a RD_N pulse, occurring in less than 60 ns after WR_N to the Endpoint Index or
Control Function register, data corruption occurs, irrespective of the CS_N signal. The
data corruption problem occurs intermittently.
Fig 32. Waveform for DC_SUSPEND/WAKEUP_N pin goes LOW but the clock is not
CH1 = XTAL1, CH2 = DC_SUSPEND/WAKEUP_N, CH3 = CS_N and CH4 =
HC_SUSPEND/WAKEUP_N
started
1
2
3
4
Ch1 2.00 V
Ch3 200 mV
Rev. 01 — 18 November 2009
CC(I/O)
Ch2 2.00 V
Ch4 200 mV
Ch3
can be available before V
CC(5V0)
CC(5V0)
M 1.00 s
and V
and V
Ch1
Ch2
Ch4
CC(I/O)
Ch2
Hi-Speed USB OTG controller
CC(I/O)
are connected to the same
CC(5V0)
supplies are available at
001aak151
2.08 V
SAF1761
. Otherwise, this
© NXP B.V. 2009. All rights reserved.
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