SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 43

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 34.
[1]
Table 35.
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31
30 to 16
15
14 to 12
11
10
9
The reserved bits should always be written with the reset value.
Symbol
ALL_ATX_RESET
-
ANA_DIGI_OC
-
DEV_DMA
COMN_INT
COMN_DMA
HW Mode Control - Hardware Mode Control register (address 0300h) bit allocation
HW Mode Control - Hardware Mode Control register (address 0300h) bit description
ANA_DIGI_
ALL_ATX_
reserved
8.3.1 HW Mode Control register
RESET
R/W
R/W
R/W
8.3 Configuration registers
R/W
31
23
OC
15
0
0
7
0
0
Table 34
DACK_
POL
R/W
R/W
R/W
R/W
30
22
14
0
0
6
0
0
Description
All ATX Reset: For debugging purposes (not used normally).
1 — Enable reset, then write back logic 0
0 — No reset
reserved; write logic 0
Analog Digital Overcurrent: This bit selects analog or digital overcurrent detection on
pins OC1_N/V
0 — Digital overcurrent
1 — Analog overcurrent
reserved; write logic 0
Device DMA: When this bit and bit 9 are set, DC_DREQ and DC_DACK peripheral
signals are selected on the HC_DREQ and HC_DACK pins.
Common IRQ: When this bit is set, DC_IRQ will be generated on the HC_IRQ pin.
Common DMA: When this bit and bit 11 are set, the DC_DREQ and DC_DACK
peripheral signals are routed to the HC_DREQ and HC_DACK pins.
shows the bit allocation of the register.
reserved
DREQ_
R/W
R/W
POL
R/W
R/W
29
21
13
0
0
5
0
0
Rev. 01 — 18 November 2009
BUS
[1]
, OC2_N and OC3_N.
R/W
R/W
R/W
R/W
12
28
20
0
0
0
4
0
reserved
reserved
DEV_DMA
reserved
R/W
[1]
[1]
11
R/W
R/W
R/W
0
27
19
0
0
3
0
[1]
COMN_IRQ
INTR_POL
R/W
10
R/W
R/W
R/W
0
26
18
0
0
2
0
Hi-Speed USB OTG controller
COMN_
LEVEL
INTR_
DMA
R/W
R/W
R/W
R/W
25
17
9
0
0
0
1
0
SAF1761
© NXP B.V. 2009. All rights reserved.
DATA_BUS
GLOBAL_
INTR_EN
_WIDTH
R/W
R/W
R/W
R/W
43 of 166
24
16
0
0
8
1
0
0