SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 26

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SAF1761_1
Product data sheet
cost. This circuit offers an easy solution at no extra hardware cost on the board. The port
power will automatically be disabled by the SAF1761 on an overcurrent event occurrence,
by de-asserting the PSWn_N signal without any software intervention.
When using the integrated analog overcurrent detection, the range of the overcurrent
detection voltage for the SAF1761 is 45 mV to 120 mV. Calculation of external
components should be based on the 45 mV value, with the actual overcurrent detection
threshold usually positioned in the middle of the interval.
For an overcurrent limit of 500 mA per port, a PMOS transistor with R
approximately 100 m is required. If a PMOS transistor with a lower R
analog overcurrent detection can be adjusted using a series resistor; see
The digital overcurrent scheme requires using an external power switch with integrated
overcurrent detection, such as LM3526, MIC2526 (2 ports) or LM3544 (4 ports). These
devices are controlled by PSWn_N signals corresponding to each port. In the case of
overcurrent occurrence, these devices will assert OCn_N signals. On OCn_N assertion,
the SAF1761 cuts off the port power by de-asserting PSWn_N. The external integrated
power switch will also automatically cut off the port power in the case of an overcurrent
event, by implementing a thermal shutdown. An internal delay filter will prevent false
overcurrent reporting because of in-rush currents when plugging a USB device. Because
of this internal delay, as soon as OCn_N is asserted, PSWn_N will switch off the external
PMOS in less than 15 ms.
Remark: If port 1 is used in OTG mode or as a dual-role device, the analog overcurrent
detection must be used, same on all three ports, because the same bit (bit 15 of the HW
Mode Control register) determines the overcurrent detection type.
Fig 6.
V
I
OC(nom)
PMOS
V
PMOS
(1) R
= V
Adjusting analog overcurrent detection limit (optional)
= 1 A
= voltage drop on PMOS
td
is optional.
OC(TRIP)
Rev. 01 — 18 November 2009
= V
5 V
TRIP(intrinsic)
REF5V
(I
SAF1761
OC(nom)
PSWn_N
R
td
), where:
Hi-Speed USB OTG controller
001aai631
OCn_N
R
td
I
OC
(1)
DSon
SAF1761
DSon
© NXP B.V. 2009. All rights reserved.
Figure
of
is used, the
6.
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