SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 148

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SAF1761_1
Product data sheet
18.3.2 Implication
18.3.3 Workaround
18.4.1 Problem description
18.4 Errata added on 2009-04-20
During a short packet transfer, the counter will always be decremented by 4 bytes or
2 bytes, depending on the bus width setting although other operations are not affected.
The problem occurs when sending the last byte. The Peripheral Controller DMA Transfer
Counter register will still be decremented by 4 bytes or 2 bytes, depending on the settings
of the bus width even though only 1 byte of data is sent. This may complicate the count
and therefore, the count that exists in DMA will not be accurate.
The implication is serious in certain applications in which the empty packet or the short
packet is considered as an error condition or termination of the transfer. For example, in
certain printer class implementations, the empty packet is considered as an error
condition and the Host Controller will try to send a command to rectify the error, which
cannot be seen by the firmware. This is because the microcontroller has already set and
enabled the DMA bit, activating the DMA transfer, and has also disabled endpoint
interrupts to reduce overhead. Because of this, whatever the Host Controller sends for
error recovery will not be seen and the system stops responding.
None
While the SAF1761 is resuming operations from deep-sleep suspend, the clock does not
start again.
When the SAF1761 is put into deep-sleep suspend mode, the chip can automatically
wake up by any one of the following methods; suspend mode here means the host and
the device are suspended and the clock is turned off (see
Fig 30. Peripheral Controller recognizing the number of bytes received
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•
•
When the SAF1761 Peripheral Controller is connected to the USB Host Controller
Any access to the SAF1761 registers by the microprocessor or microcontroller
When a device is connected to the downstream port of the SAF1761
The Peripheral Controller DMA counter shows an even number of bytes (for example, 16 byte)
instead of the correct number of transferred bytes (for example, 13 byte).
DREQ
DACK
DATA
LINES
RD
Rev. 01 — 18 November 2009
4 bytes
4 bytes
4 bytes
Hi-Speed USB OTG controller
Figure
4 bytes
31):
001aak084
SAF1761
© NXP B.V. 2009. All rights reserved.
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