SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 101

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SAF1761_1
Product data sheet
10.3.1 Address register
10.3 Peripheral controller-specific registers
Table 97.
This register sets the USB assigned address and enables the USB peripheral.
shows the bit allocation of the register.
The DEVADDR[6:0] bits will be cleared whenever a bus reset, a power-on reset or a soft
reset occurs. The DEVEN bit will be cleared whenever a power-on reset or a soft reset
occurs, and will remain unchanged on a bus reset.
Address Register
Initialization registers
0200h
020Ch
0210h
0212h
0214h
0300h
0374h
Data flow registers
022Ch
0228h
0220h
021Ch
021Eh
0204h
0208h
DMA registers
0230h
0234h
0238h
023Ch
0250h
0254h
0258h
0264h
General registers
0218h
0270h
0274h
0278h
027Ch
0280h
0284h
Address
Mode
Interrupt Configuration
Debug
DcInterruptEnable
HW Mode Control
OTG Control
Endpoint Index
Control Function
Data Port
Buffer Length
DcBufferStatus
Endpoint MaxPacketSize
Endpoint Type
DMA Command
DMA Transfer Counter
DcDMAConfiguration
DMA Hardware
DMA Interrupt Reason
DMA Interrupt Enable
DMA Endpoint
DMA Burst Counter
DcInterrupt
DcChipID
Frame Number
DcScratch
Unlock Device
Interrupt Pulse Width
Test Mode
Peripheral controller-specific register overview
Rev. 01 — 18 November 2009
Reset value
00h
0000h
FCh
0008h
0000 0000h
0000 0000h
0000 0086h
20h
00h
0000 0000h
0000h
00h
0000h
0000h
FFh
0000 0000h
0001h
04h
0000h
0000h
00h
0004h
0000 0000h
0001 1582h
0000h
0000h
0000h
001Eh
00h
Hi-Speed USB OTG controller
References
Section 10.3.1
Section 10.3.2
Section 10.3.3
Section 10.3.4
Section 10.3.5
Section 8.3.1
Section 9.5.2.1
Section 10.4.1
Section 10.4.2
Section 10.4.3
Section 10.4.4
Section 10.4.5
Section 10.4.6
Section 10.4.7
Section 10.5.2
Section 10.5.3
Section 10.5.4
Section 10.5.5
Section 10.5.6
Section 10.5.7
Section 10.5.8
Section 10.5.9
Section 10.6.1
Section 10.6.2
Section 10.6.3
Section 10.6.4
Section 10.6.5
Section 10.6.6
Section 10.6.7
SAF1761
© NXP B.V. 2009. All rights reserved.
Table 98
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