SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 51

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 51.
[1]
Table 52.
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 16
15 to 13
12
[1]
The reserved bits should always be written with the reset value.
Symbol
CLK_OFF_
COUNTER[15:0]
-
PORT3_PD
Power-Down Control register (address 0354h) bit allocation
Power-Down Control register (address 0354h) bit description
8.3.11 Power-Down Control register
R/W
R/W
R/W
R/W
31
23
15
0
1
0
7
1
reserved
This register is used to turn off power to the internal blocks of the SAF1761 to obtain
maximum power savings.
reserved
[1]
R/W
R/W
R/W
R/W
30
22
14
0
1
0
6
0
Description
Clock Off Counter: Determines the wake-up status duration after any wake-up event
before the SAF1761 goes back into suspend mode. This time-out is applicable only if,
during the given interval, the host controller is not programmed back to the normal
functionality.
03E8h — The default value. It determines the default wake-up interval of 10 ms. A value
of zero implies that the host controller never wakes up on any of the events. This may be
useful when using the SAF1761 as a peripheral to save power by permanently
programming the host controller in suspend.
FFFFh — The maximum value. It determines a maximum wake-up time of 500 ms.
The setting of this register is based on the 100 kHz
multiple of 10 s period.
Remark: In 16-bit mode, the default value is 17E8h. A write operation to these bits with
any value fixes the clock off counter at 1400h. This value is equivalent to a fixed wake-up
time of 50 ms.
reserved
Port 3 Pull-Down: Controls port 3 pull-down resistors.
0 — Port 3 internal pull-down resistors are not connected.
1 — Port 3 internal pull-down resistors are connected.
[1]
BIASEN
R/W
R/W
R/W
R/W
29
21
13
0
1
0
5
1
Rev. 01 — 18 November 2009
Table 51
CLK_OFF_COUNTER[15:8]
CLK_OFF_COUNTER[7:0]
VREG_ON
PORT3_
R/W
R/W
R/W
R/W
PD
28
20
12
0
0
1
4
0
shows the bit allocation of the register.
OC3_PWR
PORT2_
R/W
R/W
R/W
R/W
PD
27
19
11
0
1
1
3
0
VBATDET_
OC2_PWR
PWR
R/W
R/W
R/W
R/W
40 % LazyClock frequency. It is a
26
18
10
0
0
0
2
0
Hi-Speed USB OTG controller
OC1_PWR
R/W
R/W
R/W
R/W
25
17
1
0
9
1
1
0
SAF1761
© NXP B.V. 2009. All rights reserved.
reserved
HC_CLK_
[1]
R/W
R/W
R/W
R/W
EN
51 of 166
24
16
1
0
8
1
0
0