SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 57

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 59.
Table 60.
Table 61.
Table 62.
SAF1761_1
Product data sheet
Bit
31 to 0
Bit
31 to 0
Bit
31 to 0
Bit
31 to 0 ATL_IRQ_
Symbol
MASK_AND
[31:0]
Symbol
INT_IRQ_MASK_
AND[31:0]
Symbol
ATL_IRQ_MASK_
OR[31:0]
Symbol
ISO_IRQ_MASK_
AND[31:0]
ATL IRQ Mask OR register (address 0320h) bit description
ISO IRQ Mask AND register (address 0324h) bit description
INT IRQ Mask AND register (address 0328h) bit description
ATL IRQ Mask AND register (address 032Ch) bit description
8.4.5 ATL IRQ Mask OR register
8.4.6 ISO IRQ Mask AND register
8.4.7 INT IRQ Mask AND register
8.4.8 ATL IRQ Mask AND register
Each bit of this register corresponds to one of the 32 ATL PTDs defined, and is a
hardware IRQ mask for each PTD done map. See
see
Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a
hardware IRQ mask for each PTD done map. For details, see
Table 60
Each bit of this register (see
and is a hardware IRQ mask for each PTD done map. For details, see
Each bit of this register corresponds to one of the 32 ATL PTDs defined, and is a
hardware IRQ mask for each PTD done map. For details, see
Table 62
Access
R/W
Section
Access
R/W
Access Value
R/W
Access Value
R/W
provides the bit description of the register.
shows the bit description of the register.
Value
0000 0000h
7.4.
0000 0000h
0000 0000h ISO IRQ Mask AND: Represents a direct map for ISO PTDs 31 to 0.
Value
0000 0000h
Rev. 01 — 18 November 2009
Description
ATL IRQ Mask AND: Represents a direct map for ATL PTDs 31 to 0.
0 — No OR condition defined between ATL PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain AND condition between the 32 ATL PTDs.
Description
0 — No AND condition defined between ISO PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain AND condition between the 32 INT PTDs.
Description
INT IRQ Mask AND: Represents a direct map for INT PTDs 31 to 0.
0 — No OR condition defined between INT PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain AND condition between the 32 INT PTDs.
Description
ATL IRQ Mask OR: Represents a direct map for ATL PTDs 31 to 0.
0 — No OR condition defined between ATL PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain OR condition.
Table
61) corresponds to one of the 32 INT PTDs defined,
Table 59
Hi-Speed USB OTG controller
for bit description. For details,
Section
Section
7.4.
7.4.
SAF1761
Section
© NXP B.V. 2009. All rights reserved.
7.4.
57 of 166