SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 108

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 111. Addressing of endpoint buffers
Table 112. Control Function register (address 0228h) bit allocation
[1]
Table 113. Control Function register (address 0228h) bit description
SAF1761_1
Product data sheet
Buffer name
SETUP
Control OUT
Control IN
Data OUT
Data IN
Bit
Symbol
Reset
Bus reset
Access
Bit
7 to 5 -
4
3
2
The reserved bits should always be written with the reset value.
Symbol
CLBUF
VENDP
DSEN
10.4.2 Control Function register
R/W
Description
reserved
Clear Buffer: Logic 1 clears the TX or RX buffer of the indexed endpoint. The TX or RX buffer is
automatically cleared once the endpoint is completely read. This bit is set only when it is necessary to
forcefully clear the buffer.
Remark: If using double buffer, to clear both the buffers issue the CLBUF command two times.
Validate Endpoint: Logic 1 validates data in the TX FIFO of an IN endpoint for sending on the next IN
token. In general, the endpoint is automatically validated when its FIFO byte count has reached the
endpoint MaxPacketSize. This bit is set only when it is necessary to validate the endpoint with the FIFO
byte count that is below the Endpoint MaxPacketSize.
Data Stage Enable: This bit controls the response of the SAF1761 to a control transfer. After the
completion of the set-up stage, firmware must determine whether a data stage is required. For control
OUT, firmware will set this bit and the SAF1761 goes into the data stage. Otherwise, the SAF1761 will
NAK the data stage transfer. For control IN, firmware will set this bit before writing data to the TX FIFO
and validate the endpoint. If no data stage is required, firmware can immediately set the STATUS bit after
the set-up stage.
Remark: The DSEN bit is cleared once the OUT token is acknowledged by the device and the IN token
is acknowledged by the PC host. This bit cannot be read back and reading this bit will return logic 0.
7
0
0
The Control Function register performs the buffer management on endpoints. It consists
of 1 byte, and the bit configuration is given in
validate any enabled data endpoint. Before accessing this register, the Endpoint Index
register must first be written to specify the target endpoint.
reserved
R/W
6
0
0
[1]
R/W
5
0
0
Rev. 01 — 18 November 2009
EP0SETUP
1
0
0
0
0
CLBUF
R/W
4
0
0
VENDP
R/W
Table
3
0
0
ENDPIDX
00h
00h
00h
0Xh
0Xh
112. The register bits can stall, clear or
DSEN
W
2
0
0
Hi-Speed USB OTG controller
STATUS
DIR
0
0
1
0
1
R/W
1
0
0
SAF1761
© NXP B.V. 2009. All rights reserved.
STALL
108 of 166
R/W
0
0
0