SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 113

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 122. Endpoint Type register (address 0208h) bit description
SAF1761_1
Product data sheet
Bit
15 to 5
4
3
2
1 to 0
Symbol
-
NOEMPKT
ENABLE
DBLBUF
ENDPTYP[1:0]
10.5.1 GDMA read or write (opcode = 00h/01h) for Generic DMA slave mode
10.5 DMA registers
The Generic DMA (GDMA) transfer can be done by writing the proper opcode in the DMA
Command register. The control bits are given in
The GDMA (slave) can operate in counter mode. RD_N and WR_N are DMA data strobe
signals. These signals are also used as data strobe signals during the PIO access. An
internal multiplex will redirect these signals to the DMA Controller for the DMA transfer or
to registers for the PIO access.
In counter mode, the DIS_XFER_CNT bit in the DcDMAConfiguration register must be set
to logic 0. The DMA Transfer Counter register must be programmed before any DMA
command is issued. The DMA transfer counter is set by writing from the LSByte to the
MSByte (address: 234h to 237h). The DMA transfer count is internally updated only after
the MSByte is written. Once the DMA transfer is started, the transfer counter starts
decrementing and on reaching 0, the DMA_XFER_OK bit is set and an interrupt is
generated by the SAF1761.
The DMA transfer starts once the DMA command is issued. Any of the following three
ways will terminate this DMA transfer:
There are two interrupts that are programmable to differentiate the method of DMA
termination: the INT_EOT and DMA_XFER_OK bits in the DMA Interrupt Reason register.
For details, see
•
•
•
Description
reserved
No Empty Packet: Logic 0 causes the SAF1761 to return a null length packet for the IN token
after the DMA IN transfer is complete. Set to logic 1 to disable the generation of the null length
packet.
Endpoint Enable: Logic 1 enables the FIFO of the indexed endpoint. The memory size is
allocated as specified in the Endpoint MaxPacketSize register. Logic 0 disables the FIFO.
Remark: Stalling a data endpoint will confuse the Data Toggle bit on the stalled endpoint
because the internal logic picks up from where it has stalled. Therefore, the Data Toggle bit
must be reset by disabling and re-enabling the corresponding endpoint (by setting bit ENABLE
to logic 0, followed by logic 1 in the Endpoint Type register) to reset the PID.
Double Buffering: Logic 1 enables double buffering for the indexed endpoint. Logic 0 disables
double buffering.
Endpoint Type: These bits select the endpoint type as follows.
00 — Not used
01 — Isochronous
10 — Bulk
11 — Interrupt
Detecting an internal EOT (short packet on an OUT token)
Resetting the DMA
GDMA stop command
Table
Rev. 01 — 18 November 2009
135.
Table
123.
Hi-Speed USB OTG controller
SAF1761
© NXP B.V. 2009. All rights reserved.
113 of 166