SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 161

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 104.Debug mode settings . . . . . . . . . . . . . . . . . . .104
Table 105.Debug register (address 0212h)
Table 106.Debug register (address 0212h)
Table 107.DcInterruptEnable - Device Controller Interrupt
Table 108.DcInterruptEnable - Device Controller Interrupt
Table 109.Endpoint Index register (address 022Ch) bit
Table 110.Endpoint Index register (address 022Ch) bit
Table 111.Addressing of endpoint buffers . . . . . . . . . . .108
Table 112.Control Function register (address 0228h) bit
Table 113.Control Function register (address 0228h) bit
Table 114.Data Port register (address 0220h)
Table 115.Data Port register (address 0220h)
Table 116.Buffer Length register (address 021Ch) bit
Table 117.DcBufferStatus - Device Controller Buffer Status
Table 118.DcBufferStatus - Device Controller Buffer Status
Table 119.Endpoint MaxPacketSize register (address
Table 120.Endpoint MaxPacketSize register (address
Table 121.Endpoint Type register (address 0208h) bit
Table 122.Endpoint Type register (address 0208h) bit
Table 123.Control bits for GDMA read or write (opcode =
Table 124.DMA Command register (address 0230h) bit
Table 125.DMA Command register (address 0230h) bit
Table 126.DMA commands . . . . . . . . . . . . . . . . . . . . . .114
Table 127.DMA Transfer Counter register (address 0234h)
Table 128.DMA Transfer Counter register (address 0234h)
Table 129.DcDMAConfiguration - Device Controller Direct
SAF1761_1
Product data sheet
bit description . . . . . . . . . . . . . . . . . . . . . . . .104
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .104
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .105
Enable register (address 0214h)
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .105
Enable register (address 0214h)
bit description . . . . . . . . . . . . . . . . . . . . . . . .106
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
description . . . . . . . . . . . . . . . . . . . . . . . . . . .107
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
description . . . . . . . . . . . . . . . . . . . . . . . . . . .108
bit description . . . . . . . . . . . . . . . . . . . . . . . .109
bit description . . . . . . . . . . . . . . . . . . . . . . . .110
description . . . . . . . . . . . . . . . . . . . . . . . . . . .110
register (address 021Eh) bit allocation . . . . .111
register (address 021Eh) bit description . . . .111
0204h) bit allocation . . . . . . . . . . . . . . . . . . . .111
0204h) bit description . . . . . . . . . . . . . . . . . .112
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
description . . . . . . . . . . . . . . . . . . . . . . . . . . .113
00h/01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
description . . . . . . . . . . . . . . . . . . . . . . . . . . .114
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . .115
bit description . . . . . . . . . . . . . . . . . . . . . . . .116
Rev. 01 — 18 November 2009
Table 130.DcDMAConfiguration - Device Controller Direct
Table 131.DMA Hardware register (address 023Ch) bit
Table 132.DMA Hardware register (address 023Ch) bit
Table 133.DMA Interrupt Reason register (address 0250h)
Table 134.DMA Interrupt Reason register (address 0250h)
Table 135.Internal EOT-functional relation with the
Table 136.DMA Interrupt Enable register (address 0254h) bit
Table 137.DMA Endpoint register (address 0258h) bit
Table 138.DMA Endpoint register (address 0258h) bit
Table 139.DMA Burst Counter register (address 0264h) bit
Table 140.DMA Burst Counter register (address 0264h) bit
Table 141.DcInterrupt - Device Controller Interrupt register
Table 142.DcInterrupt - Device Controller Interrupt register
Table 143.DcChipID - Device Controller Chip Identifier
Table 144.Frame Number register (address 0274h) bit
Table 145.Frame Number register (address 0274h) bit
Table 146.DcScratch - Device Controller Scratch register
Table 147.DcScratch - Device Controller Scratch register
Table 148.Unlock Device register (address 027Ch) bit
Table 149.Unlock Device register (address 027Ch) bit
Table 150.Interrupt Pulse Width register (address 0280h) bit
Table 151.Test Mode register (address 0284h)
Table 152.Test Mode register (address 0284h) bit
Table 153.Power consumption, typical values . . . . . . . . 125
Table 154.Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 126
Memory Access Configuration register (address
0238h) bit allocation . . . . . . . . . . . . . . . . . . . 116
Memory Access Configuration register (address
0238h) bit description . . . . . . . . . . . . . . . . . . 116
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . 118
bit description . . . . . . . . . . . . . . . . . . . . . . . . 118
DMA_XFER_OK bit . . . . . . . . . . . . . . . . . . . . 118
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
(address 0218h) bit allocation . . . . . . . . . . . . 121
(address 0218h) bit description . . . . . . . . . . . 121
register (address 0270h) bit description . . . . 122
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
(address 0278h) bit allocation . . . . . . . . . . . . 123
(address 0278h) bit description . . . . . . . . . . . 123
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . 124
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Hi-Speed USB OTG controller
SAF1761
© NXP B.V. 2009. All rights reserved.
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