SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 18

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SAF1761_1
Product data sheet
Fig 5.
USB BUS
Memory segmentation and access block diagram
AND LOW-SPEED)
USB HIGH-SPEED
TRANSACTION
TRANSLATOR
(FULL-SPEED
HOST AND
The RAM is structured in blocks of PTDs and payloads so that while the USB is executing
on an active transfer-based PTD, the processor can simultaneously fill up another block
area in the RAM. A PTD and its payload can then be updated on-the-fly without stopping
or delaying any other USB transaction or corrupting the RAM data.
Some of the design features are:
•
•
•
•
The address range of the internal RAM buffer is from 0400h to FFFFh.
The internal memory contains isochronous, interrupt and asynchronous PTDs, and
respective defined payloads.
All accesses to the internal memory are double word aligned.
Internal memory address range calculation:
Memory address = (CPU address
63 kB
address
data (64 bits)
control signals
PAYLOAD
PAYLOAD
ARBITER
PTD32
PTD32
PTD32
PTD1
PTD2
PTD1
PTD2
PTD1
PTD2
Rev. 01 — 18 November 2009
240 MB/s
ASYNC
PAYLOAD
ISOCHRONOUS
INTERRUPT
0400h) (shift right >> 3). Base address is 0400h.
MEMORY MAPPED
INPUT/OUTPUT,
MANAGEMENT
CONTROLLER
INTERRUPT
REGISTERS
SLAVE DMA
CONTROL
MEMORY
UNIT,
AND
Hi-Speed USB OTG controller
D[15:0]/D[31:0]
DC_DREQ
HC_DREQ
HC_DACK
DC_DACK
DC_IRQ
HC_IRQ
A[17:1]
CS_N
RD_N
WR_N
SAF1761
© NXP B.V. 2009. All rights reserved.
PROCESSOR
MICRO-
004aaa568
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