SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 56

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 56.
Table 57.
Table 58.
SAF1761_1
Product data sheet
Bit
7
6
5
4
3
2
1
0
Bit
31 to 0
Bit
31 to 0
Symbol
ISO_IRQ_MASK_
OR[31:0]
Symbol
INT_IRQ_MASK_
OR[31:0]
Symbol
INT_IRQ_E
CLKREADY_E
HCSUSP_E
-
DMAEOTINT_E DMA EOT Interrupt Enable: Controls assertion of IRQ on the DMA transfer completion.
-
SOFITLINT_E
-
HcInterruptEnable - Host Controller Interrupt Enable register (address 0314h) bit description
ISO IRQ Mask OR register (address 0318h) bit description
INT IRQ Mask OR register (address 031Ch) bit description
8.4.3 ISO IRQ Mask OR register
8.4.4 INT IRQ Mask OR register
Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a
hardware IRQ mask for each PTD done map. See
see
Each bit of this register (see
and is a hardware IRQ mask for each PTD done map. For details, see
Description
INT IRQ Enable: Controls the IRQ assertion when one or more INT PTDs matching the INT
IRQ Mask AND or INT IRQ Mask OR register bits combination are completed.
0 — No IRQ will be asserted when INT PTDs are completed
1 — IRQ will be asserted
For details, see
Clock Ready Enable: Enables the IRQ assertion when internal clock signals are running
stable. Useful after wake-up.
0 — No IRQ will be generated after a CLKREADY_E event
1 — IRQ will be generated after a CLKREADY_E event
Host Controller Suspend Enable: Enables the IRQ generation when the host controller
enters suspend mode.
0 — No IRQ will be generated when the host controller enters suspend mode
1 — IRQ will be generated when the host controller enters suspend mode
reserved; write reset value
0 — No IRQ will be generated when a DMA transfer is completed
1 — IRQ will be asserted when a DMA transfer is completed
reserved; write reset value
SOT ITL Interrupt Enable: Controls the IRQ generation at every SOF occurrence.
0 — No IRQ will be generated on SOF occurrence
1 — IRQ will be asserted at every SOF
reserved; write reset value
Section
Access Value
R/W
Access Value
R/W
7.4.
0000 0000h
0000 0000h
Section
Rev. 01 — 18 November 2009
7.4.
Description
ISO IRQ Mask OR: Represents a direct map for ISO PTDs 31 to 0.
0 — No OR condition defined between ISO PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain OR condition.
Description
INT IRQ Mask OR: Represents a direct map for INT PTDs 31 to 0.
0 — No OR condition defined between INT PTDs 31 to 0.
1 — The bits corresponding to certain PTDs are set to logic 1 to
define a certain OR condition.
Table
58) corresponds to one of the 32 INT PTDs defined,
Table 57
Hi-Speed USB OTG controller
for bit description. For details,
SAF1761
Section
© NXP B.V. 2009. All rights reserved.
…continued
7.4.
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