SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 102

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 98.
Table 99.
Table 100. Mode register (address 020Ch) bit allocation
[1]
[2]
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
7
6 to 0
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
The reserved bits should always be written with the reset value.
The value depends on the status of the V
Symbol
DEVEN
DEVADDR[6:0]
Address register (address 0200h) bit allocation
Address register (address 0200h) bit description
unchanged
10.3.2 Mode register
CLKAON
unchanged
DEVEN
R/W
R/W
15
R/W
0
0
7
0
7
0
In response to standard USB request SET_ADDRESS, firmware must write the (enabled)
peripheral address to the Address register, followed by sending an empty packet to the
host. The new peripheral address is activated when the peripheral receives
acknowledgment from the host for the empty packet token.
This register consists of 2 bytes (bit allocation: see
The Mode register controls resume, suspend and wake-up behavior, interrupt activity, soft
reset and clock signals.
SNDRSU
Description
Device Enable: Logic 1 enables the device. The device will not respond to the host, unless
this bit is set.
Device Address: This field specifies the USB device peripheral.
R/W
R/W
14
0
0
6
0
0
R/W
6
0
0
BUS
GOSUSP
pin.
R/W
R/W
13
0
0
5
0
0
R/W
Rev. 01 — 18 November 2009
5
0
0
reserved
SFRESET
[1]
R/W
R/W
12
R/W
0
0
4
0
0
4
0
0
DEVADDR[6:0]
GLINTENA
unchanged
R/W
R/W
11
R/W
0
0
3
0
3
0
0
Table
WKUPCS
R/W
R/W
R/W
10
100).
0
0
2
0
0
Hi-Speed USB OTG controller
2
0
0
unchanged
DMACLK
R/W
R/W
R/W
ON
9
0
0
1
0
SAF1761
1
0
0
© NXP B.V. 2009. All rights reserved.
reserved
VBUSSTAT
unchanged
[1]
102 of 166
R/W
R/W
R/W
0
0
8
0
0
0
0
0
[2]
[2]