SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 162

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 155.Recommended operating conditions . . . . . . .126
Table 156.Static characteristics: digital pins . . . . . . . . . .127
Table 157.Static characteristics: pins PSW1_N,
Table 158.Static characteristics: POR . . . . . . . . . . . . . .127
Table 159.Static characteristics: pin REF5V . . . . . . . . .127
Table 160.Static characteristics: USB interface block
Table 161.Static characteristics: V
Table 162.Static characteristics: V
Table 163.Dynamic characteristics: system
Table 164.Dynamic characteristics:
Table 165.Dynamic characteristics:
Table 166.Dynamic characteristics:
Table 167.Dynamic characteristics:
Table 168.Register or memory write . . . . . . . . . . . . . . .132
Table 169.Register read . . . . . . . . . . . . . . . . . . . . . . . . .133
Table 170.Register access . . . . . . . . . . . . . . . . . . . . . . .134
Table 171.Memory read . . . . . . . . . . . . . . . . . . . . . . . . .134
Table 172.DMA read (single cycle) . . . . . . . . . . . . . . . . .135
Table 173.DMA write (single cycle) . . . . . . . . . . . . . . . .136
Table 174.DMA read (multi-cycle burst) . . . . . . . . . . . . .137
Table 175.DMA write (multi-cycle burst) . . . . . . . . . . . . .138
Table 176.PIO register read or write . . . . . . . . . . . . . . .139
Table 177.Register access . . . . . . . . . . . . . . . . . . . . . . .140
Table 178.DMA read or write . . . . . . . . . . . . . . . . . . . . .141
Table 179.SnPb eutectic process (from J-STD-020C) . .145
Table 180.Lead-free process (from J-STD-020C) . . . . .145
Table 181.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .155
Table 182.Revision history . . . . . . . . . . . . . . . . . . . . . . .157
SAF1761_1
Product data sheet
PSW2_N and PSW3_N . . . . . . . . . . . . . . . . .127
(pins DM1 to DM3 and DP1 to DP3) . . . . . . .128
clock timing . . . . . . . . . . . . . . . . . . . . . . . . . .130
CPU interface block . . . . . . . . . . . . . . . . . . . .130
high-speed source electrical characteristics .130
full-speed source electrical characteristics . .131
low-speed source electrical characteristics . .131
BUS
BUS
comparators . . . .129
resistors . . . . . . .129
Rev. 01 — 18 November 2009
Hi-Speed USB OTG controller
SAF1761
© NXP B.V. 2009. All rights reserved.
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