SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 39

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 23.
[1]
Table 24.
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 20
19 to 16
15 to 14
13
12
11 to 10
9
8
7
6
5 to 3
The reserved bits should always be written with the reset value.
Symbol
-
PTC[3:0]
PIC[1:0]
PO
PP
LS[1:0]
-
PR
SUSP
FPR
-
PORTSC1 - Port Status and Control 1 register (address 0064h) bit allocation
PORTSC1 - Port Status and Control 1 register (address 0064h) bit description
SUSP
R/W
R/W
R/W
31
23
15
R
0
0
0
7
0
PIC[1:0]
Description
reserved
Port Test Control: When this field is zero, the port is not operating in test mode. A nonzero
value indicates that it is operating in test mode indicated by the value.
Port Indicator Control: Writing to this field has no effect if the P_INDICATOR bit in the
HCSPARAMS register is logic 0.
For a description on how these bits are implemented, refer to
Specification Rev.
Port Owner: This bit unconditionally goes to logic 0 when the configured bit in the
CONFIGFLAG register makes a logic 0 to logic 1 transition. This bit unconditionally goes to
logic 1 whenever the configured bit is logic 0.
Port Power: The function of this bit depends on the value of the Port Power Control (PPC) field
in the HCSPARAMS register.
Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10)
signal lines.
reserved
Port Reset: Logic 1 means the port is in the reset state. Logic 0 means the port is not in
reset.
Suspend: Logic 1 means the port is in the suspend state. Logic 0 means the port is not
suspended.
Force Port Resume: Logic 1 means resume detected or driven on the port. Logic 0 means no
resume (K-state) detected or driven on the port.
reserved
FPR
R/W
R/W
R/W
30
22
14
R
0
0
0
6
0
[2]
reserved
[2]
[1]
[1]
R/W
R/W
R/W
R/W
PO
29
21
13
0
0
1
5
0
2.0”.
Rev. 01 — 18 November 2009
[2]
reserved
R/W
R/W
R/W
R/W
PP
28
20
12
0
0
0
4
0
reserved
[1]
[1]
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
[2]
LS[1:0]
PED
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
Hi-Speed USB OTG controller
Ref. 1 “Universal Serial Bus
PTC[3:0]
reserved
ECSC
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
SAF1761
© NXP B.V. 2009. All rights reserved.
[1]
ECCS
R/W
R/W
PR
39 of 166
24
16
R
R
0
0
8
0
0
0