SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 163

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
26. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. Internal power-on reset timing . . . . . . . . . . . . . . .30
Fig 11. Clock with respect to the external
Fig 12. NextPTD traversal rule. . . . . . . . . . . . . . . . . . . . .59
Fig 13. HNP sequence of events . . . . . . . . . . . . . . . . . . .86
Fig 14. Dual-role A-device state diagram. . . . . . . . . . . . .88
Fig 15. Dual-role B-device state diagram. . . . . . . . . . . . .89
Fig 16. USB source differential data-to-EOP transition
Fig 17. Register or memory write. . . . . . . . . . . . . . . . . .132
Fig 18. Register read . . . . . . . . . . . . . . . . . . . . . . . . . . .133
Fig 19. Register access . . . . . . . . . . . . . . . . . . . . . . . . .133
Fig 20. Memory read . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Fig 21. DMA read (single cycle). . . . . . . . . . . . . . . . . . .135
Fig 22. DMA write (single cycle) . . . . . . . . . . . . . . . . . .136
Fig 23. DMA read (multi-cycle burst) . . . . . . . . . . . . . . .137
Fig 24. DMA write (multi-cycle burst) . . . . . . . . . . . . . . .138
Fig 25. SAF1761 register access timing: separate
Fig 26. PIO register access . . . . . . . . . . . . . . . . . . . . . .140
Fig 27. DMA read or write . . . . . . . . . . . . . . . . . . . . . . .141
Fig 28. Package outline SOT425-1 (LQFP128) . . . . . . .143
Fig 29. Temperature profiles for large and small
Fig 30. Peripheral Controller recognizing
Fig 31. Waveform for deep-sleep suspend . . . . . . . . . .149
Fig 32. Waveform for DC_SUSPEND/WAKEUP_N
Fig 33. Timing diagram for reading Endpoint Index
SAF1761_1
Product data sheet
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pin configuration (LQFP128); top view . . . . . . . . .7
Internal hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
SAF1761 clock scheme . . . . . . . . . . . . . . . . . . . .15
Memory segmentation and access
block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Adjusting analog overcurrent detection limit
(optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
SAF1761 power supply connection . . . . . . . . . . .27
Most commonly used power supply connection .28
Hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . .30
skew and EOP width . . . . . . . . . . . . . . . . . . . . .131
address and data buses (8051 style). . . . . . . . .139
components . . . . . . . . . . . . . . . . . . . . . . . . . . . .146
the number of bytes received. . . . . . . . . . . . . . .148
pin goes LOW but the clock is not started . . . . .150
register after performing a write access. . . . . . .151
Rev. 01 — 18 November 2009
Hi-Speed USB OTG controller
SAF1761
© NXP B.V. 2009. All rights reserved.
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