SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 103

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 101. Mode register (address 020Ch) bit description
SAF1761_1
Product data sheet
Bit
15 to 10
9
8
7
6
5
4
3
2
1 to 0
Symbol
-
DMACLKON
VBUSSTAT
CLKAON
SNDRSU
GOSUSP
SFRESET
GLINTENA
WKUPCS
-
10.3.3 Interrupt Configuration register
This 1 byte register determines the behavior and polarity of the INT output. The bit
allocation is shown in
or NYET, it will generate interrupts depending on three Debug mode fields.
CDBGMOD[1:0] — Interrupts for the control endpoint 0
DDBGMODIN[1:0] — Interrupts for the DATA IN endpoints 1 to 7
DDBGMODOUT[1:0] — Interrupts for the DATA OUT endpoints 1 to 7
The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow you
to individually configure when the SAF1761 sends an interrupt to the external
microprocessor.
Description
reserved
DMA Clock On:
1 — Supply clock to the DMA circuit.
0 — Power saving mode. The DMA circuit will stop completely to save power.
V
When implementing a pure host or peripheral, the OTG_DISABLE bit in the OTG Control
register (374h) must be set to logic 1 so that the VBUSSTAT bit is updated with the correct
value.
Clock Always On:
1 — Enable the Clock-Always-On feature
0 — Disable the Clock-Always-On feature
When the Clock-Always-On feature is disabled, a GOSUSP event can stop the clock. The clock
is stopped after a delay of approximately 2 ms. Therefore, the peripheral controller will
consume less power.
If the Clock-Always-On feature is enabled, clocks are always running and the GOSUSP event
is unable to stop the clock while the peripheral controller enters the suspend state.
Send Resume: Writing logic 1, followed by logic 0 will generate an upstream resume signal of
10 ms duration, after a 5 ms delay.
Go Suspend: Writing logic 1, followed by logic 0 will activate suspend mode.
Soft Reset: Writing logic 1, followed by logic 0 will enable a software-initiated reset to the
SAF1761. A soft reset is similar to a hardware-initiated reset using the RESET_N pin.
Global Interrupt Enable: Logic 1 enables all interrupts. Individual interrupts can be masked
by clearing the corresponding bits in the DcInterruptEnable register.
When this bit is not set, an unmasked interrupt will not generate an interrupt trigger on the
interrupt pin. If the global interrupt, however, is enabled while there is any pending unmasked
interrupt, an interrupt signal will immediately be generated on the interrupt pin. If the interrupt
is set to pulse mode, the interrupt events that were generated before the global interrupt is
enabled may be dropped.
Wake up on Chip Select: Logic 1 enables wake-up through a valid register read on the
SAF1761. A read will invoke the chip clock to restart. A write to the register before the clock is
stable may cause malfunctioning.
reserved
BUS
Status: This bit reflects the V
Table 104
Rev. 01 — 18 November 2009
Table
lists the available combinations.
102. When the USB SIE receives or generates an ACK, NAK
BUS
pin status.
Hi-Speed USB OTG controller
SAF1761
© NXP B.V. 2009. All rights reserved.
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