SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 107

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 109. Endpoint Index register (address 022Ch) bit allocation
[1]
Table 110. Endpoint Index register (address 022Ch) bit description
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
7 to 6
5
4 to 1
0
The reserved bits should always be written with the reset value.
Symbol
-
EP0SETUP
ENDPIDX[3:0]
DIR
10.4.1 Endpoint Index register
10.4 Data flow registers
R/W
7
0
0
reserved
The Endpoint Index register selects a target endpoint for register access by the
microcontroller. The register consists of 1 byte, and the bit allocation is shown in
Table
The following registers are indexed:
For example, to access the OUT data buffer of endpoint 1 using the Data Port register, the
Endpoint Index register must be written first with 02h.
Remark: The Endpoint Index register and the DMA Endpoint register must not point to the
same endpoint, irrespective of IN and OUT.
•
•
•
•
•
•
Description
reserved
Endpoint 0 Set up: Selects the SETUP buffer for endpoint 0.
0 — Data buffer
1 — SETUP buffer
Must be logic 0 for access to endpoints other than set-up token buffer.
Endpoint Index: Selects the target endpoint for register access of buffer length, buffer status,
control function, data port, endpoint type and MaxPacketSize.
Direction bit: Sets the target endpoint as IN or OUT.
0 — Target endpoint refers to OUT (RX) FIFO
1 — Target endpoint refers to IN (TX) FIFO
Buffer Length
DcBufferStatus
Control Function
Data Port
Endpoint MaxPacketSize
Endpoint Type
[1]
109.
R/W
6
0
0
EP0SETUP
unchanged
R/W
5
1
Rev. 01 — 18 November 2009
R/W
4
0
0
R/W
3
0
0
ENDPIDX[3:0]
R/W
2
0
0
Hi-Speed USB OTG controller
R/W
1
0
0
SAF1761
© NXP B.V. 2009. All rights reserved.
107 of 166
R/W
DIR
0
0
0