SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 90

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SAF1761_1
Product data sheet
9.5 OTG controller registers
The following steps are required to enable an OTG interrupt:
When an interrupt is generated on HC_IRQ, perform these steps in the interrupt service
routine to get the related OTG status:
The OTG state machine routines are called when any of the inputs is changed. These
inputs come from either OTG registers (hardware) or application program (software). The
outputs of the state machine include control signals to the OTG register (for hardware)
and states or error codes (for software).
The SAF1761 can be configured in OTG mode or in pure host or peripheral mode.
Programming the SAF1761 in OTG mode is done by configuring bit 10 of the OTG control
register. This will enable OTG-specific mechanisms controlled by the OTG control register
bits.
When the OTG protocol is not implemented by the software, the SAF1761 can be used as
a host or a peripheral. In this case, bit 10 of the OTG control register will be set to logic 0.
The host or peripheral functionality is determined by bit 7 of the OTG Control register.
Programming of OTG registers is done by a SET and RESET scheme. An OTG register
has two parts: a 16-bit SET and a 16-bit RESET. Writing logic 1 in a certain position to the
SET-type dedicated 16-bit register part will set the respective bit to logic 1 while writing
logic 1 to the RESET-type 16-bit dedicated register will change the corresponding bit to
logic 0.
Table 79.
Table 80.
Address
037Xh to 038Xh OTG registers
Address
Device ID registers
0370h
OTG Control register
0374h
1. Set the polarity and level-triggering or edge-triggering mode of the HW Mode Control
2. Set the corresponding bits of the OTG Interrupt Enable Rise and OTG Interrupt
3. Set bit OTG_IRQ_E of the HcInterruptEnable register (bit 10).
4. Set bit GLOBAL_INTR_EN of the HW Mode Control register (bit 0).
1. Read the HcInterrupt register. If OTG_IRQ (bit 10) is set, then step 2.
2. Read the OTG Interrupt Latch register. If any of the bits 0 to 4 are set, then step 3.
3. Read the OTG Status register.
register.
Enable Fall registers.
OTG controller-specific register overview
Address mapping of registers: 32-bit data bus mode
Register
Byte 3
Product ID (read only)
OTG Control (clear)
Rev. 01 — 18 November 2009
Byte 2
Reset value
-
Byte 1
Vendor ID (read only)
OTG Control (set)
Hi-Speed USB OTG controller
References
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SAF1761
© NXP B.V. 2009. All rights reserved.
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