SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 25

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SAF1761_1
Product data sheet
7.7 Overcurrent detection
HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N require pull-up resistors
because in the SAF1761 suspended state these pins become 3-state and can be pulled
down, driving them externally by switching the processors GPIO lines to output mode to
generate the SAF1761 wake-up.
The HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N pins are 3-state
output and also input to the internal wake-up logic.
When in suspend mode, the SAF1761 internal wake-up circuitry will sense the status of
the HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N pins:
The resume state has a clock-off count timer defined by bits 31 to 16 of the Power-Down
Control register. The default value of this timer is 10 ms, meaning that the resume state
will be maintained for 10 ms. If during this time, the RUN/STOP bit in the USBCMD
register is set to logic 1, the host controller will go into a permanent resume; the normal
functional state. If the RUN/STOP bit is not set during the time determined by the clock-off
count, the SAF1761 will switch back to suspend mode after the specified time. The
maximum delay that can be programmed in the clock-off count field is approximately
500 ms.
The Power-Down Control register allows additionally the SAF1761 internal blocks to be
disabled for lower power consumption as defined in
A very low suspend current can be achieved by completely switching off the V
an external PMOS transistor, controlled by one of the GPIO pins of the processor.
When the SAF1761 power is always on, the time from wake-up to suspend will be
approximately 100 ms.
It is necessary to wait for the CLKREADY interrupt assertion before programming the
SAF1761 because internal clocks are stopped during deep-sleep suspend and restarted
after the first wake-up event. The occurrence of the CLKREADY interrupt means that
internal clocks are running and the normal functionality is achieved.
It is estimated that the CLKREADY interrupt will be generated less than 100 s after the
wake-up event, if the power to the SAF1761 was on during suspend.
If the SAF1761 is used in hybrid mode and V
pulse is required when the power is switched back on, before the resume programming
sequence starts. This will ensure that internal clocks are running and all logics reach a
stable initial state.
The SAF1761 can implement a digital or analog overcurrent detection scheme. Bit 15 of
the HW Mode Control register can be programmed to select the analog or digital
overcurrent detection. An analog overcurrent detection circuit is integrated on-chip. The
main features of this circuit are self reporting, automatic resetting, low-trip time and low
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If the pins remain pulled-up, no wake-up will be generated because a HIGH is sensed
by the internal wake-up circuit.
If the pins are externally pulled LOW, for example, by the GPIO lines or just a test by
jumpers, the input to the wake-up circuitry becomes LOW and the wake-up is
internally initiated.
Rev. 01 — 18 November 2009
CC(5V0)
Section
is off during suspend, a 3 ms reset
Hi-Speed USB OTG controller
8.3.11.
SAF1761
© NXP B.V. 2009. All rights reserved.
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