SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 124

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 149. Unlock Device register (address 027Ch) bit description
Table 150. Interrupt Pulse Width register (address 0280h) bit description
Table 151. Test Mode register (address 0284h) bit allocation
[1]
Table 152. Test Mode register (address 0284h) bit description
SAF1761_1
Product data sheet
Bit
15 to 0
Bit
15 to 0
Bit
Symbol
Reset
Bus reset
Access
Bit
7
6 to 5
4
3
2
1
0
The reserved bits should always be written with the reset value.
Symbol
INTR_PULSE_
WIDTH[15:0]
Symbol
ULCODE[15:0]
Symbol
FORCEHS
-
FORCEFS
PRBS
KSTATE
JSTATE
SE0_NAK
10.6.6 Interrupt Pulse Width register
10.6.7 Test Mode register
unchanged
FORCEHS
R/W
7
0
Table 150
This 1 byte register allows the firmware to set the DP and DM pins to predetermined
states for testing purposes. The bit allocation is given in
Remark: Only one bit can be set to logic 1 at a time.
[1]
[2]
Either FORCEHS or FORCEFS must be set at a time.
Of the four bits, PRBS, KSTATE, JSTATE and SE0_NAK, only one bit must be set at a time.
Access
R/W
Description
Unlock Code: Writing data AA37h unlocks internal registers and FIFOs for writing, following
a resume.
Description
Force High-Speed: Logic 1
the chirp detection logic.
reserved.
Force Full-Speed: Logic 1
the chirp detection logic.
Logic 1
K State: Writing logic 1
J State: Writing logic 1
SE0 NAK: Writing logic 1
device only responds to a valid high-speed IN token with a NAK.
R/W
6
0
0
shows the bit description of the register.
reserved
[2]
Value
001Eh Interrupt Pulse Width: The interrupt signal pulse width is configurable
sets pins DP and DM to toggle in a predetermined random pattern.
[1]
R/W
Rev. 01 — 18 November 2009
Description
while it is in pulse signaling mode. The minimum pulse width is 3.33 ns
when this register is set to logic 1. The power-on reset value of 1Eh allows
a pulse of 1 s to be generated.
5
0
0
[2]
[2]
sets the DP and DM pins to the J state.
[2]
sets the DP and DM pins to the K state.
unchanged
FORCEFS
[1]
[1]
sets pins DP and DM to a high-speed quiescent state. The
R/W
forces the physical layer to full-speed mode only and disables
forces the hardware to high-speed mode only and disables
4
0
PRBS
R/W
3
0
0
KSTATE
Table
R/W
Hi-Speed USB OTG controller
2
0
0
151.
JSTATE
R/W
SAF1761
1
0
0
© NXP B.V. 2009. All rights reserved.
SE0_NAK
124 of 166
R/W
0
0
0