SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 119

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 136. DMA Interrupt Enable register (address 0254h) bit allocation
[1]
Table 137. DMA Endpoint register (address 0258h) bit allocation
[1]
Table 138. DMA Endpoint register (address 0258h) bit description
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
7 to 4
3 to 1
0
The reserved bits should always be written with the reset value.
The reserved bits should always be written with the reset value.
Symbol
-
EPIDX[2:0]
DMADIR
10.5.7 DMA Interrupt Enable register
10.5.8 DMA Endpoint register
R/W
R/W
R/W
15
0
0
7
0
0
7
0
0
This 2 bytes register controls the interrupt generation of the source bits in the DMA
Interrupt Reason register. The bit allocation is given in
given in
Logic 1 enables the interrupt generation. The values after a (bus) reset are logic 0
(disabled).
This 1 byte register selects a USB endpoint FIFO as the source or destination for DMA
transfers. The bit allocation is given in
The DMA Endpoint register must not reference the endpoint that is indexed by the
Endpoint Index register (022Ch) at any time. Doing so will result in data corruption.
Therefore, if the DMA Endpoint register is unused, point it to an unused endpoint. If the
DMA Endpoint register, however, is pointed to an active endpoint, the firmware must not
reference the same endpoint on the Endpoint Index register.
reserved
Description
reserved
Selects the indicated endpoint for DMA access
DMA Direction:
0 — Selects the RX/OUT FIFO for DMA write transfers
1 — Selects the TX/IN FIFO for DMA read transfers
R/W
R/W
R/W
14
0
0
6
0
0
6
0
0
Table
reserved
[1]
134.
[1]
R/W
R/W
R/W
13
0
0
5
0
0
5
0
0
Rev. 01 — 18 November 2009
IE_GDMA_
STOP
R/W
R/W
R/W
12
0
0
4
0
0
4
0
0
reserved
Table
reserved
[1]
R/W
R/W
R/W
137.
11
0
0
3
0
0
3
0
0
[1]
EPIDX[2:0]
IE_INT_
Table
EOT
R/W
R/W
R/W
10
0
0
2
0
0
2
0
0
Hi-Speed USB OTG controller
136. The bit description is
reserved
R/W
R/W
R/W
9
0
0
1
0
0
1
0
0
SAF1761
© NXP B.V. 2009. All rights reserved.
[1]
XFER_OK
IE_DMA_
DMADIR
119 of 166
R/W
R/W
R/W
8
0
0
0
0
0
0
0
0