SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 54

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 54.
SAF1761_1
Product data sheet
Bit
31 to 11
10
9
8
7
6
5
4
3
2
1
0
Symbol
-
OTG_IRQ
ISO_IRQ
ATL_IRQ
INT_IRQ
CLKREADY
HCSUSP
-
DMAEOTINT
-
SOFITLINT
-
HcInterrupt - Host Controller Interrupt register (address 0310h) bit description
Description
reserved; write reset value
OTG_IRQ: Indicates that an OTG event occurred. The IRQ line will be asserted if the
respective enable bit in the HcInterruptEnable register is set.
0 — No OTG event
1 — OTG event occurred
For details, see
ISO IRQ: Indicates that an ISO PTD was completed, or the PTDs corresponding to the bits set
in the ISO IRQ Mask AND or ISO IRQ Mask OR register bits combination were completed. The
IRQ line will be asserted if the respective enable bit in the HcInterruptEnable register is set.
0 — No ISO PTD event occurred
1 — ISO PTD event occurred
For details, see
ATL IRQ: Indicates that an ATL PTD was completed, or the PTDs corresponding to the bits set
in the ATL IRQ Mask AND or ATL IRQ Mask OR register bits combination were completed. The
IRQ line will be asserted if the respective enable bit in the HcInterruptEnable register is set.
0 — No ATL PTD event occurred
1 — ATL PTD event occurred
For details, see
INT IRQ: Indicates that an INT PTD was completed, or the PTDs corresponding to the bits set
in the INT IRQ Mask AND or INT IRQ Mask OR register bits combination were completed. The
IRQ line will be asserted if the respective enable bit in the HcInterruptEnable register is set.
0 — No INT PTD event occurred
1 — INT PTD event occurred
For details, see
Clock Ready: Indicates that internal clock signals are running stable. The IRQ line will be
asserted if the respective enable bit in the HcInterruptEnable register is set.
0 — No CLKREADY event has occurred
1 — CLKREADY event occurred
Host Controller Suspend: Indicates that the host controller has entered suspend mode. The
IRQ line will be asserted if the respective enable bit in the HcInterruptEnable register is set.
0 — The host controller did not enter suspend mode.
1 — The host controller entered suspend mode.
If the Interrupt Service Routine (ISR) accesses the SAF1761, it will wake up for the time
specified in bits 31 to 16 of the Power-Down Control register.
reserved; write reset value
DMA EOT Interrupt: Indicates the DMA transfer completion. The IRQ line will be asserted if
the respective enable bit in the HcInterruptEnable register is set.
0 — No DMA transfer is completed
1 — DMA transfer is completed
reserved; write reset value; value is zero just after reset and changes to one after a short while
SOT ITL Interrupt: The IRQ line will be asserted if the respective enable bit in the
HcInterruptEnable register is set.
0 — No SOF event has occurred
1 — An SOF event has occurred
reserved; write reset value; value is zero just after reset and changes to one after a short while
Section
Section
Section
Section
Rev. 01 — 18 November 2009
7.4.
7.4.
7.4.
7.4.
Hi-Speed USB OTG controller
SAF1761
© NXP B.V. 2009. All rights reserved.
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