SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 34

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 13.
Table 14.
[1]
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 16
15 to 8
7 to 4
3
2
1
0
For details on register bit description, refer to
Symbol
-
EECP[7:0]
IST[3:0]
-
ASPC
PFLF
-
HCCPARAMS - Host Controller Capability Parameters register (address 0008h) bit allocation
HCCPARAMS - Host Controller Capability Parameters register (address 0008h) bit description
8.1.4 HCCPARAMS register
31
23
15
R
R
R
R
0
0
0
7
1
The Host Controller Capability Parameters (HCCPARAMS) register is a four byte register,
and the bit allocation is given in
Description
reserved; write logic 0
EHCI Extended Capabilities Pointer: Default = implementation dependent. This optional field
indicates the existence of a capabilities list.
Isochronous Scheduling Threshold: Default = implementation dependent. This field
indicates, relative to the current position of the executing host controller, where software can
reliably update the isochronous schedule.
reserved; write logic 0
Asynchronous Schedule Park Capability: Default = implementation dependent. If this bit is
set to logic 1, the host controller supports the park feature for high-speed Transfer Descriptors
in the Asynchronous Schedule.
Programmable Frame List Flag: Default = implementation dependent. If this bit is cleared,
the system software must use a frame list length of 1024 elements with this host controller.
If PFLF is set, the system software can specify and use a smaller frame list and configure the
host through the Frame List Size (FLS) field of the USBCMD register.
reserved; write logic 0
30
22
14
R
R
R
R
0
0
0
6
0
IST[3:0]
[1]
Ref. 2 “Enhanced Host Controller Interface Specification for Universal Serial Bus Rev.
29
21
13
R
R
R
R
0
0
0
5
0
Rev. 01 — 18 November 2009
Table
28
20
12
R
R
R
R
0
0
0
4
0
EECP[7:0]
reserved
reserved
13.
reserved
27
19
11
R
R
R
R
0
0
0
3
0
ASPC
26
18
10
R
R
R
R
0
0
0
2
1
Hi-Speed USB OTG controller
PFLF
25
17
R
R
R
R
0
0
9
0
1
1
SAF1761
© NXP B.V. 2009. All rights reserved.
reserved
34 of 166
24
16
R
R
R
R
0
0
8
0
0
0
1.0”.