SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 121

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 141. DcInterrupt - Device Controller Interrupt register (address 0218h) bit allocation
[1]
Table 142. DcInterrupt - Device Controller Interrupt register (address 0218h) bit description
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
31 to 26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
The reserved bits should always be written with the reset value.
Symbol
-
EP7TX
EP7RX
EP6TX
EP6RX
EP5TX
EP5RX
EP4TX
EP4RX
EP3TX
EP3RX
EP2TX
EP2RX
EP1TX
EP1RX
EP0TX
EP0RX
EP6TX
EP2TX
VBUS
R/W
R/W
R/W
R/W
31
23
15
0
0
0
0
0
0
7
0
0
Description
reserved
logic 1 indicates the endpoint 7 TX buffer as interrupt source
logic 1 indicates the endpoint 7 RX buffer as interrupt source
logic 1 indicates the endpoint 6 TX buffer as interrupt source
logic 1 indicates the endpoint 6 RX buffer as interrupt source
logic 1 indicates the endpoint 5 TX buffer as interrupt source
logic 1 indicates the endpoint 5 RX buffer as interrupt source
logic 1 indicates the endpoint 4 TX buffer as interrupt source
logic 1 indicates the endpoint 4 RX buffer as interrupt source
logic 1 indicates the endpoint 3 TX buffer as interrupt source
logic 1 indicates the endpoint 3 RX buffer as interrupt source
logic 1 indicates the endpoint 2 TX buffer as interrupt source
logic 1 indicates the endpoint 2 RX buffer as interrupt source
logic 1 indicates the endpoint 1 TX buffer as interrupt source
logic 1 indicates the endpoint 1 RX buffer as interrupt source
logic 1 indicates the endpoint 0 data TX buffer as interrupt source
logic 1 indicates the endpoint 0 data RX buffer as interrupt source
EP6RX
EP2RX
DMA
R/W
R/W
R/W
R/W
30
22
14
0
0
0
0
0
0
6
0
0
HS_STAT
EP5TX
EP1TX
R/W
R/W
R/W
R/W
29
21
13
0
0
0
0
0
0
5
0
0
Rev. 01 — 18 November 2009
reserved
RESUME
EP5RX
EP1RX
[1]
R/W
R/W
R/W
R/W
28
20
12
0
0
0
0
0
0
4
0
0
EP4TX
EP0TX
SUSP
R/W
R/W
R/W
R/W
27
19
11
0
0
0
0
0
0
3
0
0
EP4RX
EP0RX
PSOF
R/W
R/W
R/W
R/W
26
18
10
0
0
0
0
0
0
2
0
0
Hi-Speed USB OTG controller
reserved
EP7TX
EP3TX
R/W
SOF
R/W
R/W
R/W
25
17
9
0
0
0
0
0
0
1
0
0
SAF1761
© NXP B.V. 2009. All rights reserved.
[1]
EP0SETUP
BRESET
EP7RX
EP3RX
121 of 166
R/W
R/W
R/W
R/W
24
16
8
0
0
0
0
0
0
0
0
1