SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 109

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 113. Control Function register (address 0228h) bit description
Table 114. Data Port register (address 0220h) bit description
SAF1761_1
Product data sheet
Bit
1
0
Bit
31 to 0
Symbol
STATUS
STALL
Symbol
DATAPORT
[31:0]
10.4.3 Data Port register
Description
Status Acknowledge: Only applicable for control IN and OUT.
This bit controls the generation of ACK or NAK during the status stage of a SETUP transfer. It is
automatically cleared when the status stage is completed and a SETUP token is received. No interrupt
signal will be generated.
0 — Sends NAK
1 — Sends an empty packet following the IN token (peripheral-to-host) or ACK following the OUT token
(host-to-peripheral)
Remark: The STATUS bit is cleared to zero once the zero-length packet is acknowledged by the device
or the PC host.
Remark: Data transfers preceding the status stage must first be fully completed before the STATUS bit
can be set.
Stall Endpoint: Logic 1 stalls the indexed endpoint. This bit is not applicable for isochronous transfers.
Remark: Stalling a data endpoint will confuse the Data Toggle bit about the stalled endpoint because the
internal logic picks up from where it is stalled. Therefore, the Data Toggle bit must be reset by disabling
and re-enabling the corresponding endpoint (by setting bit ENABLE to logic 0, followed by logic 1 in the
Endpoint Type register) to reset the PID.
This register provides direct access for a microcontroller to the FIFO of the indexed
endpoint.
Peripheral to host (IN endpoint): After each write, an internal counter is automatically
incremented, by two in 16-bit mode and four in 32-bit mode, to the next location in the TX
FIFO. When all bytes have been written (FIFO byte count = endpoint MaxPacketSize), the
buffer is automatically validated. The data packet will then be sent on the next IN token.
Whenever required, the Control Function register (bit VENDP) can validate the endpoint
whose byte count is less than MaxPacketSize.
Remark: The buffer can automatically be validated using the Buffer Length register.
Host to peripheral (OUT endpoint): After each read, an internal counter is automatically
decremented, by two in 16-bit mode and four in 32-bit mode, to the next location in the RX
FIFO. When all bytes have been read, the buffer contents are automatically cleared. A
new data packet can then be received on the next OUT token. Buffer contents can also be
cleared through the Control Function register (bit CLBUF), whenever it is necessary to
forcefully clear contents.
The Data Port register description when the SAF1761 is in 32-bit mode is given in
Table
Access
R/W
The Data Port register description when the SAF1761 is in 16-bit mode is given in
Table
114.
115.
Value
0000 0000h
Rev. 01 — 18 November 2009
Description
Data Port: A 500 ns delay starting from the reception of the endpoint
interrupt may be required for the first read from the data port.
…continued
Hi-Speed USB OTG controller
SAF1761
© NXP B.V. 2009. All rights reserved.
109 of 166