SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 44
SAF1761BE/V1,518
Manufacturer Part Number
SAF1761BE/V1,518
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SAF1761BEV1518.pdf
(166 pages)
Specifications of SAF1761BE/V1,518
Lead Free Status / Rohs Status
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Table 35.
Table 36.
SAF1761_1
Product data sheet
Bit
8
7
6
5
4 to 3
2
1
0
Bit
31 to 0
Symbol
DATA_BUS_WIDTH
-
DACK_POL
DREQ_POL
-
INTR_POL
INTR_LEVEL
GLOBAL_INTR_EN
HW Mode Control - Hardware Mode Control register (address 0300h) bit description
HcChipID - Host Controller Chip Identifier register (address 0304h) bit description
Symbol
CHIPID[31:0]
8.3.2 HcChipID register
Read this register to get the ID of the SAF1761. The upper word of the register contains
the hardware version number and the lower word contains the chip ID.
bit description of the register.
Access
R
Description
Data Bus Width:
0 — Defines a 16-bit data bus width
1 — Sets a 32-bit data bus width
Remark: Setting this bit will affect all the controllers on the chip: host controller, peripheral
controller and OTG controller.
reserved; write logic 0
DACK Polarity:
1 — Indicates that the DACK input is active HIGH
0 — Indicates active LOW
DREQ Polarity:
1 — Indicates that the DREQ output is active HIGH
0 — Indicates active LOW
reserved; write logic 0
Interrupt Polarity:
0 — Active LOW
1 — Active HIGH
Interrupt Level:
0 — INT is level triggered.
1 — INT is edge triggered. A pulse of certain width is generated.
Global Interrupt Enable: This bit must be set to logic 1 to enable IRQ signal assertion.
0 — IRQ assertion disabled. IRQ will never be asserted, regardless of other settings or
IRQ events.
1 — IRQ assertion enabled. IRQ will be asserted according to the HcInterruptEnable
register, and events setting and occurrence.
Value
0001 1761h
Rev. 01 — 18 November 2009
Description
Chip ID: This register represents the hardware version number
(0001h) and the chip ID (1761h).
Remark: The chip ID is for internal use to identify the SAF176x
product family.
Hi-Speed USB OTG controller
…continued
Table 36
SAF1761
© NXP B.V. 2009. All rights reserved.
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