SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 58

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
SAF1761_1
Product data sheet
8.5 Proprietary Transfer Descriptor (PTD)
The standard EHCI data structures as described in
Interface Specification for Universal Serial Bus Rev. 1.0”
operation that is managed by the hardware state machine.
The PTD structures of the SAF1761 are translations of the EHCI data structures that are
optimized for the SAF1761. It, however, still follows the basic EHCI architecture. This
optimized form of EHCI data structures is necessary because the SAF1761 is a slave host
controller and has no bus master capability.
EHCI manages schedules in two lists: periodic and asynchronous. The data structures
are designed to provide the maximum flexibility required by USB, minimize memory traffic,
and reduce hardware and software complexity. The SAF1761 controller executes
transactions for devices by using a simple shared-memory schedule. This schedule
consists of data structures organized into three lists:
qISO — Isochronous transfer
qINTL — Interrupt transfer
qATL — Asynchronous transfer; for the control and bulk transfers
The system software maintains two lists for the host controller: periodic and
asynchronous.
The SAF1761 has a maximum of 32 ISO, 32 INTL and 32 ATL PTDs. These PTDs are
used as channels to transfer data from the shared memory to the USB bus. These
channels are allocated and de-allocated on receiving the transfer from the core USB
driver.
Multiple transfers are scheduled to the shared memory for various endpoints by traversing
the next link pointer provided by endpoint data structures, until it reaches the end of the
endpoint list. There are three endpoint lists: one for ISO endpoints, and the other for INTL
and ATL endpoints. If the schedule is enabled, the host controller executes the ISO
schedule, followed by the INTL schedule, and then the ATL schedule.
These lists are traversed and scheduled by the software according to the EHCI traversal
rule. The host controller executes the scheduled ISO, INTL and ATL PTDs. The
completion of a transfer is indicated to the software by the interrupt that can be grouped
under various PTDs by using the AND or OR registers that are available for each schedule
type: ISO, INTL and ATL. These registers are simple logic registers to decide the
completion status of group and individual PTDs. When the logical conditions of the Done
bit is true in the shared memory, it means that PTD has completed.
There are four types of interrupts in the SAF1761: ISO, INTL, ATL and SOF. The latency
can be programmed in multiples of SOF (125 s).
The NextPTD pointer is a feature that allows the SAF1761 to jump unused and skip PTDs.
This will improve the PTD transversal latency time. The NextPTD pointer is not meant for
same or single endpoint. The NextPTD works only in forward direction.
The NextPTD traversal rules defined by the SAF1761 hardware are:
1. Start the PTD memory vertical traversal, considering the skip and LastPTD
information, as follows.
Rev. 01 — 18 November 2009
Ref. 2 “Enhanced Host Controller
are optimized for the bus master
Hi-Speed USB OTG controller
SAF1761
© NXP B.V. 2009. All rights reserved.
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