SAF1761BE/V1,518 NXP Semiconductors, SAF1761BE/V1,518 Datasheet - Page 116

• Manufacturer Part Number: SAF1761BE/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAF1761BE/V1,518

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 128. DMA Transfer Counter register (address 0234h) bit description
Table 129. DcDMAConfiguration - Device Controller Direct Memory Access Configuration register (address 0238h)
[1]
Table 130. DcDMAConfiguration - Device Controller Direct Memory Access Configuration register (address 0238h)
SAF1761_1
Product data sheet
Bit
Symbol
Reset
Bus reset
Access
Bit
31 to 24
23 to 16
15 to 8
7 to 0
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Bit
15 to 8
7
6 to 4
The reserved bits should always be written with the reset value.
bit allocation
bit description
Symbol
DMACR4, DMACR[31:24]
DMACR3, DMACR[23:16]
DMACR2, DMACR[15:8]
DMACR1, DMACR[7:0]
Symbol
-
DIS_XFER_CNT
-
10.5.4 DcDMAConfiguration register
XFER_CNT
R/W
DIS_
R/W
15
0
0
R/W
7
0
0
7
0
0
This register defines the DMA configuration for GDMA mode. The DcDMAConfiguration
register consists of 2 bytes. The bit allocation is given in
R/W
R/W
14
0
0
R/W
6
0
0
Description
reserved
Disable Transfer Counter: Write logic 0 to perform DMA operation. Logic 1 disables the
DMA transfer counter (see
reserved
6
0
0
reserved
R/W
R/W
13
0
0
5
0
0
R/W
Rev. 01 — 18 November 2009
5
0
0
Description
DMA Counter 4: DMA transfer counter byte 4
DMA Counter 3: DMA transfer counter byte 3
DMA Counter 2: DMA transfer counter byte 2
DMA Counter 1: DMA transfer counter byte 1
[1]
DMACR1 = DMACR[7:0]
R/W
R/W
12
R/W
0
0
4
0
0
Table
4
0
0
reserved
127).
[1]
R/W
R/W
11
R/W
0
0
3
0
0
3
0
0
MODE[1:0]
R/W
R/W
Table
R/W
10
0
0
2
0
0
Hi-Speed USB OTG controller
2
0
0
129.
reserved
R/W
R/W
R/W
9
0
0
1
0
0
SAF1761
1
0
0
© NXP B.V. 2009. All rights reserved.
WIDTH
116 of 166
R/W
R/W
R/W
8
0
0
0
1
1
0
0
0